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(WIP): SR Latch

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This commit is contained in:
Yuri Tatishchev 2024-10-19 15:20:23 -07:00
parent 8dbdebb9ce
commit d217faf166
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
1 changed files with 7 additions and 1 deletions
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8
logic.v
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@ -95,7 +95,13 @@ input S, R, C;
input nP, nR; input nP, nR;
output Q,Qbar; output Q,Qbar;
// TBD wire r1, r2;
nand n1(r1, C, S);
nand n2(r2, C, R);
nand n3(Q, nP, r1, Qbar);
nand n4(Qbar, nR, r2, Q);
endmodule endmodule