From d217faf1669836c43dfdf48213d9f8d5cece135b Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Sat, 19 Oct 2024 15:20:23 -0700 Subject: [PATCH] (WIP): SR Latch --- logic.v | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/logic.v b/logic.v index 7588cd9..a575ad1 100644 --- a/logic.v +++ b/logic.v @@ -95,7 +95,13 @@ input S, R, C; input nP, nR; output Q,Qbar; -// TBD +wire r1, r2; + +nand n1(r1, C, S); +nand n2(r2, C, R); + +nand n3(Q, nP, r1, Qbar); +nand n4(Qbar, nR, r2, Q); endmodule