lab-03: clean up twos complement modules

lab-02: fix behavioral xor statement in RC_ADD_SUB modules
lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement
2024-10-03 21:14:33 -07:00 · 2024-10-03 20:25:36 -07:00 · 2024-10-03 20:21:30 -07:00 · 2024-10-02 16:18:00 -07:00 · 2024-10-01 20:42:02 -07:00 · 2024-10-01 11:01:17 -07:00
10 changed files with 33 additions and 518 deletions
--- a/TESTBENCH/mult_tb.v
+++ b/TESTBENCH/mult_tb.v
@@ -36,8 +36,6 @@ A=10; B=20;     // Y = 10 * 20 = 200
 #1 result[i] = {HI,LO}; i=i+1;
 #1 A=10; B=19; 	// Y = 10 * 19 = 190
 #1 result[i] = {HI,LO}; i=i+1;
-#1 A=32'h00d96027; B=32'h7c32b43c; 	// Y = 0x0d96027 * 0x7c32b43c = 0x 006975a0 b62bf524
-#1 result[i] = {HI,LO}; i=i+1;
 #1 A=32'h70000000; B=32'h70000000; 
 #1 result[i] = {HI,LO}; i=i+1;
 #1 
--- a/TESTBENCH/register_file_tb.v
+++ b/TESTBENCH/register_file_tb.v
@@ -68,53 +68,24 @@ no_of_pass = 0;
 // Write cycle
 for(i=0;i<32; i = i + 1)
 begin
-#10     DATA_REG = i * 10; READ=1'b0; WRITE=1'b1; ADDR_W = i;
+#10     DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
 end

 #5 READ=1'b0; WRITE=1'b0;
 // test of write data
 for(i=0;i<32; i = i + 1)
 begin
-#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i % 7;
+#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
 #5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== i * 10)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 10, DATA_R1);
-        else if (DATA_R2 !== (i % 7) * 10)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, (i % 7) * 10, DATA_R2);
+        if (DATA_R1 !== i)
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
        else 
 	    no_of_pass  = no_of_pass + 1;
        result[ridx] = DATA_R1; ridx=ridx+1;
+        result[ridx] = DATA_R1; ridx=ridx+1;
        
 end

-// Testing read and write at the same time
-for(i=2;i<16; i = i + 1)
-begin
-#5      DATA_REG = 20; READ=1'b1; WRITE=1'b1; ADDR_W = i + 1; ADDR_R1 = i; ADDR_R2 = i * 2;
-#5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== 20)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, 20, DATA_R1);
-        else if (DATA_R2 !== i * 20)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 20, DATA_R2);
-        else
-	    no_of_pass  = no_of_pass + 1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
-
-end
-
-// Test reading when READ=0
-#5     READ=1'b0;
-#5     no_of_test = no_of_test + 1;
-if (DATA_R1 !== 32'bx)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
-else if (DATA_R2 !== 32'bx)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
-else
-no_of_pass  = no_of_pass + 1;
-result[ridx] = DATA_R1; ridx=ridx+1;
-
-// TODO: Read and write from the same address at the same time?
-// TODO: Write when WRITE=0 should be tested

 #5    READ=1'b0; WRITE=1'b0; // No op

--- a/alu.v
+++ b/alu.v
@@ -31,57 +31,7 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;

-wire [31:0] res,
-            res_addsub, res_slt,
-            res_shift,
-            res_mul,
-            res_and, res_or, res_nor;
+// TBD

-// add = xx0001
-// sub = xx0010
-// slt = xx1001
-//         ^ ^ these bits
-// can use oprn[1] or oprn[3] for SnA
-wire SnA;
-or (SnA, OPRN[1], OPRN[3]);
-RC_ADD_SUB_32 addsub(.Y(res_addsub), .CO(), .A(OP1), .B(OP2), .SnA(SnA));
-buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
-
-// shift_r = xx0100
-// shift_l = xx0101
-//                ^ this bit
-// can use oprn[0] for LnR
-SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
-
-// mul = xx0011
-MULT32 mul(.LO(res_mul), .HI(), .A(OP1), .B(OP2));
-
-// and = xx0110
-// or  = xx0111
-// nor = xx1000
-AND32_2x1 and32(res_and, OP1, OP2);
-OR32_2x1 or32(res_or, OP1, OP2);
-NOR32_2x1 nor32(res_nor, OP1, OP2);
-
-MUX32_16x1 out(.Y(res), .S(OPRN[3:0]), .I0(),
-               .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
-               .I4(res_shift),.I5(res_shift),
-               .I6(res_and), .I7(res_or), .I8(res_nor),
-               .I9(res_slt),
-               .I10(), .I11(), .I12(), .I13(), .I14(), .I15()
-);
-
-// or bits of result for zero flag
-wire nzf [31:0];
-buf (nzf[0], res[0]);
-genvar i;
-generate
-    for (i = 1; i < 32; i = i + 1) begin : zf_gen
-        or (nzf[i], nzf[i-1], res[i]);
-    end
-endgenerate
-
-not (ZERO, nzf[31]);
-buf res_out [31:0] (OUT, res);

 endmodule
--- a/barrel_shifter.v
+++ b/barrel_shifter.v
@@ -21,21 +21,7 @@ input [31:0] D;
 input [31:0] S;
 input LnR;

-// check if upper bits are nonzero
-wire oob [31:5];
-buf (oob[5], S[5]);
-genvar i;
-generate
-    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
-        or (oob[i], oob[i-1], S[i]);
-    end
-endgenerate
-
-wire [31:0] shifted;
-BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
-
-// return 0 if S >= 32
-MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
+// TBD

 endmodule

@@ -48,11 +34,7 @@ input [31:0] D;
 input [4:0] S;
 input LnR;

-wire [31:0] shifters [1:0];
-SHIFT32_R shifter_r(shifters[0], D, S);
-SHIFT32_L shifter_l(shifters[1], D, S);
-
-MUX32_2x1 mux_lnr(Y, shifters[0], shifters[1], LnR);
+// TBD

 endmodule

@@ -64,22 +46,7 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;

-wire [31:0] stages [5:0];
-buf stage0[31:0] (stages[0], D);
-
-genvar i, j;
-generate
-    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
-        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
-            if (j < 32 - (2 ** i))
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j + (2 ** i)], S[i]);
-            else
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
-        end
-    end
-endgenerate
-
-buf out[31:0] (Y, stages[5]);
+// TBD

 endmodule

@@ -91,22 +58,7 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;

-
-wire [31:0] stages [5:0];
-buf stage0[31:0] (stages[0], D);
-
-genvar i, j;
-generate
-    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
-        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
-            if (j >= (2 ** i))
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j - (2 ** i)], S[i]);
-            else
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
-        end
-    end
-endgenerate
-
-buf out[31:0] (Y, stages[5]);
+// TBD

 endmodule
+
--- a/data_path.v
+++ b/data_path.v
@@ -29,149 +29,6 @@ input [`CTRL_WIDTH_INDEX_LIMIT:0]  CTRL;
 input CLK, RST;
 input [`DATA_INDEX_LIMIT:0] DATA_IN;

-wire pc_load, pc_sel_1, pc_sel_2, pc_sel_3,
-    ir_load, reg_r, reg_w,
-    r1_sel_1, wa_sel_1, wa_sel_2, wa_sel_3,
-
-    sp_load, op1_sel_1,
-    op2_sel_1, op2_sel_2, op2_sel_3, op2_sel_4,
-
-    wd_sel_1, wd_sel_2, wd_sel_3,
-    ma_sel_1, ma_sel_2,
-    md_sel_1;
-
-wire [5:0] alu_oprn;
-
-buf (pc_load, CTRL[0]);
-buf (pc_sel_1, CTRL[1]);
-buf (pc_sel_2, CTRL[2]);
-buf (pc_sel_3, CTRL[3]);
-
-buf (ir_load, CTRL[4]);
-buf (reg_r, CTRL[5]);
-buf (reg_w, CTRL[6]);
-
-buf (r1_sel_1, CTRL[7]);
-buf (wa_sel_1, CTRL[8]);
-buf (wa_sel_2, CTRL[9]);
-buf (wa_sel_3, CTRL[10]);
-
-buf (sp_load, CTRL[11]);
-buf (op1_sel_1, CTRL[12]);
-
-buf (op2_sel_1, CTRL[13]);
-buf (op2_sel_2, CTRL[14]);
-buf (op2_sel_3, CTRL[15]);
-buf (op2_sel_4, CTRL[16]);
-
-buf (wd_sel_1, CTRL[17]);
-buf (wd_sel_2, CTRL[18]);
-buf (wd_sel_3, CTRL[19]);
-
-buf (ma_sel_1, CTRL[20]);
-buf (ma_sel_2, CTRL[21]);
-
-buf (md_sel_1, CTRL[22]);
-
-buf alu_oprn_buf [5:0] (alu_oprn, CTRL[28:23]);
-
-// variables
-wire [31:0] ir; // Instruction Register
-wire [31:0] r1, r2; // Register File
-wire [31:0] pc, pc_inc; // Program Counter
-wire [31:0] sp; // Stack Pointer
-wire [31:0] alu_out; // ALU output
-
-// TODO: Why?
-buf ir_buf [31:0] (INSTRUCTION, ir);
-
-// Parse the instruction data
-wire [5:0]   opcode;
-wire [4:0]   rs;
-wire [4:0]   rt;
-wire [4:0]   rd;
-wire [4:0]   shamt;
-wire [5:0]   funct;
-wire [15:0]  imm;
-wire [25:0]  addr;
-
-// common for all
-buf opcode_buf [5:0] (opcode, ir[31:26]);
-// common for R-type, I-type
-buf rs_buf [4:0] (rs, ir[25:21]);
-buf rt_buf [4:0] (rt, ir[20:16]);
-// for R-type
-buf rd_buf [4:0] (rd, ir[15:11]);
-buf shamt_buf [4:0] (shamt, ir[10:6]);
-buf funct_buf [5:0] (funct, ir[5:0]);
-// for I-type
-buf imm_buf [15:0] (imm, ir[15:0]);
-// for J-type
-buf addr_buf [25:0] (addr, ir[25:0]);
-
-
-// Instruction Register input
-// Instruction Register
-REG32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(ir_load), .CLK(CLK), .RESET(RST));
-
-// Register File Input
-wire [31:0] r1_sel, wa_sel, wd_sel;
-wire [31:0] wa_sel_p1, wa_sel_p2, wd_sel_p1, wd_sel_p2;
-wire [31:0] imm_zx_lsb;
-buf imm_zx_lsb_buf [31:0] (imm_zx_lsb, {imm, 16'b0});
-MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, r1_sel_1);
-MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, wa_sel_1);
-// TODO: Why 31?
-MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, wa_sel_2);
-MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, wa_sel_3);
-MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, wd_sel_1);
-MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, wd_sel_2);
-MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, wd_sel_3);
-// Register File
-REGISTER_FILE_32x32 rf_inst(.DATA_R1(r1), .DATA_R2(r2), .ADDR_R1(r1_sel[4:0]), .ADDR_R2(rt),
-                            .DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(reg_r), .WRITE(reg_w), .CLK(CLK), .RST(RST));
-
-// ALU Input
-wire [31:0] op1_sel, op2_sel;
-wire [31:0] op2_sel_p1, op2_sel_p2, op2_sel_p3;
-wire [31:0] shamt_zx, imm_sx, imm_zx;
-buf shamt_zx_buf [31:0] (shamt_zx, {27'b0, shamt});
-buf imm_sx_buf [31:0] (imm_sx, {{16{imm[15]}}, imm});
-buf imm_zx_buf [31:0] (imm_zx, {16'b0, imm});
-MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, op1_sel_1);
-MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, op2_sel_1);
-MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, op2_sel_2);
-MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, op2_sel_3);
-MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, op2_sel_4);
-// ALU
-ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(alu_oprn));
-
-// Progam Counter Input
-wire [31:0] pc_sel;
-wire [31:0] pc_offset, pc_jump, pc_sel_p1, pc_sel_p2;
-RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0));
-MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, pc_sel_1);
-RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_offset), .CO(), .A(pc), .B(imm_sx), .SnA(1'b0));
-MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_offset, pc_sel_2);
-buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr});
-MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, pc_sel_3);
-// Program Counter
-defparam pc_inst.PATTERN = `INST_START_ADDR;
-REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(pc_load), .CLK(CLK), .RESET(RST));
-
-// Stack Pointer
-defparam sp_inst.PATTERN = `INIT_STACK_POINTER;
-REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(sp_load), .CLK(CLK), .RESET(RST));
-
-// Data out
-MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, md_sel_1);
-
-// Address out
-wire [31:0] ma_sel_p1;
-MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, ma_sel_1);
-// TODO: Check address calculation since it's 26 bit
-(* keep="soft" *)
-wire [5:0] _addr_ignored;
-MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, ma_sel_2);
+// TBD

 endmodule
--- a/logic.v
+++ b/logic.v
@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;

-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(), .A(64'b0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));

 endmodule

@@ -31,31 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;

-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(), .A(0), .B(A), .SnA(1'b1));
-
-endmodule
-
-// 32-bit register with parameterized preset pattern
-module REG32_PP(Q, D, LOAD, CLK, RESET);
-parameter PATTERN = 32'h00000000;
-output [31:0] Q;
-
-input CLK, LOAD;
-input [31:0] D;
-input RESET;
-
-wire [31:0] qbar;
-
-genvar i;
-generate
-    for(i=0; i<32; i=i+1)
-    begin : reg32_gen_loop
-       if (PATTERN[i] == 0)
-              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(1'b1), .nR(RESET));
-        else
-              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(RESET), .nR(1'b1));
-    end
-endgenerate
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));

 endmodule

@@ -67,12 +43,7 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;

-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1) begin : reg_gen
-        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
-    end
-endgenerate
+// TBD

 endmodule

@@ -85,10 +56,7 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;

-wire D_out;
-MUX1_2x1 data(D_out, Q, D, L);
-
-D_FF dff(Q, Qbar, D_out, C, nP, nR);
+// TBD

 endmodule

@@ -101,11 +69,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;

-wire Cbar, Y, Ybar;
-not C_inv(Cbar, C);
-D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
-
-SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
+// TBD

 endmodule

@@ -118,10 +82,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;

-wire Dbar;
-not D_inv(Dbar, D);
-
-SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
+// TBD

 endmodule

@@ -134,13 +95,7 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;

-wire r1, r2;
-
-nand n1(r1, C, S);
-nand n2(r2, C, R);
-
-nand n3(Q, nP, r1, Qbar);
-nand n4(Qbar, nR, r2, Q);
+// TBD

 endmodule

@@ -151,19 +106,7 @@ output [31:0] D;
 // input
 input [4:0] I;

-wire [15:0] half;
-wire I_not;
-not I_inv(I_not, I[4]);
-
-DECODER_4x16 d(half, I[3:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 16; i = i + 1) begin : d5_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 16], I[4], half[i]);
-    end
-endgenerate
+// TBD

 endmodule

@@ -174,19 +117,7 @@ output [15:0] D;
 // input
 input [3:0] I;

-wire [7:0] half;
-wire I_not;
-not I_inv(I_not, I[3]);
-
-DECODER_3x8 d(half, I[2:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 8; i = i + 1) begin : d4_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 8], I[3], half[i]);
-    end
-endgenerate
+// TBD


 endmodule
@@ -198,19 +129,8 @@ output [7:0] D;
 // input
 input [2:0] I;

-wire [3:0] half;
-wire I_not;
-not I_inv(I_not, I[2]);
+//TBD

-DECODER_2x4 d(half, I[1:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 4; i = i + 1) begin : d3_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 4], I[2], half[i]);
-    end
-endgenerate

 endmodule

@@ -221,12 +141,6 @@ output [3:0] D;
 // input
 input [1:0] I;

-wire I_not [1:0];
-not I_inv[1:0] (I_not, I);
-
-and (D[0], I_not[1], I_not[0]);
-and (D[1], I_not[1], I[0]);
-and (D[2], I[1], I_not[0]);
-and (D[3], I[1], I[0]);
+// TBD

 endmodule
--- a/logic_32_bit.v
+++ b/logic_32_bit.v
@@ -80,19 +80,3 @@ generate
    end
 endgenerate
 endmodule
-
-// 32-bit buffer
-module BUF32_1x1(Y,A);
-//output 
-output [31:0] Y;
-//input
-input [31:0] A;
-
-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1)
-    begin : buf32_gen_loop
-        buf buf32_inst(Y[i], A[i]);
-    end
-endgenerate
-endmodule
--- a/mult.v
+++ b/mult.v
@@ -27,25 +27,7 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;

-wire [31:0] A_neg, B_neg;
-TWOSCOMP32 A_twoscomp(A_neg, A);
-TWOSCOMP32 B_twoscomp(B_neg, B);
-
-wire [31:0] A_abs, B_abs;
-MUX32_2x1 A_mux(A_abs, A, A_neg, A[31]);
-MUX32_2x1 B_mux(B_abs, B, B_neg, B[31]);
-
-wire [31:0] HI_abs, LO_abs;
-MULT32_U mult_abs(HI_abs, LO_abs, A_abs, B_abs);
-
-wire [31:0] HI_neg, LO_neg;
-TWOSCOMP64 mult_neg({HI_neg,LO_neg}, {HI_abs,LO_abs});
-
-wire sign;
-xor (sign, A[31], B[31]);
-
-MUX32_2x1 HI_mux(HI, HI_abs, HI_neg, sign);
-MUX32_2x1 LO_mux(LO, LO_abs, LO_neg, sign);
+// TBD

 endmodule

@@ -57,37 +39,6 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;

-// partial sums
-wire [31:0] Y [31:0];
-
-// first partial is just
-AND32_2x1 partial_1(Y[0], A, {32{B[0]}});
-// put lowest bit from first partial into result
-buf (LO[0], Y[0][0]);
-
-
-// carries from partial adders
-wire CI[31:0];
-// first carry is always 0
-buf (CI[0], 0);
-
-genvar i;
-generate
-    for (i = 0; i < 31; i = i + 1)
-    begin : mult32u_gen_loop
-        // multiply A by a single digit in B
-        wire [31:0] A_and;
-        AND32_2x1 partial_and_inst(A_and, A, {32{B[i+1]}});
-
-        // calc the next partial and carry (i + 1)
-        RC_ADD_SUB_32 partial_add_inst(.Y(Y[i+1]), .CO(CI[i+1]), .A(A_and), .B({CI[i],Y[i][31:1]}), .SnA(1'b0));
-
-        // put lowest bit from calc into result
-        buf (LO[i+1], Y[i+1][0]);
-    end
-endgenerate
-
-// last carry and partial is HI
-BUF32_1x1 buf_hi(HI, {CI[31],Y[31][31:1]});
+// TBD

 endmodule
--- a/mux.v
+++ b/mux.v
@@ -27,16 +27,7 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
 input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
 input [4:0] S;

-wire [31:0] x0, x1;
-MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
-                       I8, I9, I10, I11, I12, I13, I14, I15,
-                       S[3:0]
-);
-MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
-                       I24, I25, I26, I27, I28, I29, I30, I31,
-                       S[3:0]
-);
-MUX32_2x1 out(Y, x0, x1, S[4]);
+// TBD

 endmodule

@@ -64,11 +55,7 @@ input [31:0] I14;
 input [31:0] I15;
 input [3:0] S;

-
-wire [31:0] x0, x1;
-MUX32_8x1 mux8_0(x0, I0, I1, I2, I3, I4, I5, I6, I7, S[2:0]);
-MUX32_8x1 mux8_1(x1, I8, I9, I10, I11, I12, I13, I14, I15, S[2:0]);
-MUX32_2x1 out(Y, x0, x1, S[3]);
+// TBD

 endmodule

@@ -87,10 +74,7 @@ input [31:0] I6;
 input [31:0] I7;
 input [2:0] S;

-wire [31:0] x0, x1;
-MUX32_4x1 mux4_0(x0, I0, I1, I2, I3, S[1:0]);
-MUX32_4x1 mux4_1(x1, I4, I5, I6, I7, S[1:0]);
-MUX32_2x1 out(Y, x0, x1, S[2]);
+// TBD

 endmodule

@@ -105,10 +89,7 @@ input [31:0] I2;
 input [31:0] I3;
 input [1:0] S;

-wire [31:0] x0, x1;
-MUX32_2x1 mux2_0(x0, I0, I1, S[0]);
-MUX32_2x1 mux2_1(x1, I2, I3, S[0]);
-MUX32_2x1 out(Y, x0, x1, S[1]);
+// TBD

 endmodule

@@ -121,22 +102,7 @@ input [31:0] I0;
 input [31:0] I1;
 input S;

-// only need 1 not gate
-wire S_not;
-not (S_not, S);
-
-// wire [31:0] x0, x1;
-
-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1)
-    begin : mux32_gen_loop
-        wire x0, x1;
-        and (x0, S_not, I0[i]);
-        and (x1, S, I1[i]);
-        or (Y[i], x0, x1);
-    end
-endgenerate
+// TBD

 endmodule

@@ -147,10 +113,6 @@ output Y;
 //input list
 input I0, I1, S;

-wire S_not, x0, x1;
-not (S_not, S);
-and (x0, S_not, I0);
-and (x1, S, I1);
-or (Y, x0, x1);
+// TBD

 endmodule
--- a/register_file.v
+++ b/register_file.v
@@ -41,30 +41,6 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;

-wire [31:0] Q [31:0];
-wire [31:0] r_write_sel, r_write;
-DECODER_5x32 d_write(r_write_sel, ADDR_W);
-
-// only write when WRITE=1
-and write_active [31:0] (r_write, r_write_sel, WRITE);
-
-REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
-
-wire [31:0] r1, r2;
-MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
-                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
-                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
-                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
-                     ADDR_R1
-);
-MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
-                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
-                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
-                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
-                     ADDR_R2
-);
-
-MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
-MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
+// TBD

 endmodule
Author	SHA1	Message	Date
Yuri Tatishchev	f4a3e3bb8b	lab-03: clean up twos complement modules	2024-10-03 21:14:33 -07:00
Yuri Tatishchev	f5b19ae9fc	lab-02: fix behavioral xor statement in RC_ADD_SUB modules	2024-10-03 20:25:36 -07:00
Yuri Tatishchev	48bdad0e8b	lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement	2024-10-03 20:21:30 -07:00
Yuri Tatishchev	bb7e172316	implement a Verilog gate level model for 64-bit Ripple Carry Adder and 32/64-bit twos complement Gate level implementation for the following components: - RC_ADD_SUB_64 - TWOSCOMP64 - TWOSCOMP32	2024-10-02 16:18:00 -07:00
Iurii Tatishchev	3801d523de	implement a Verilog gate level model for ripple carry adder subtractor Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32	2024-10-01 20:42:02 -07:00
Iurii Tatishchev	d1475b5a4f	implement a Verilog gate level model for ripple carry adder subtractor Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32	2024-10-01 11:01:17 -07:00