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compare: CaZzzer:b651f04748acdeff63a6a19453c0ea2acc9fd087
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2 Commits
05c950a0f8 ... b651f04748

Author SHA1 Message Date
Yuri Tatishchev
b651f04748
control unit: more progress, fibonacci working 2024-11-18 00:47:16 -08:00
Yuri Tatishchev
2ffd8c9424
da vinci tb: patch for smaller (20-bit) memory for faster tests 2024-11-18 00:46:22 -08:00
12 changed files with 86 additions and 79 deletions
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12
OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat
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@ -1,9 +1,9 @@
// memory data file (do not edit the following line - required for mem load use) // memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000 00000001
00000000 00000004
00000000 00000004
00000000 00000010
00000000 00000010
00000000 00000040

2
OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat
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@ -6,4 +6,4 @@
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000200

22
OUTPUT/CS147_SP17_HW01_02_mem_dump.dat
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@ -1,14 +1,14 @@
// memory data file (do not edit the following line - required for mem load use) // memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000000a 00090001
0000000b 00090003
0000000c 00090005
0000000d 00090007
0000000e 00090009
0000000f 0009000b
00000010 0009000d
00000011 0009000f
00000012 00090011
00000013 00090013
00000000 00090015

2
OUTPUT/RevFib_mem_dump.dat
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@ -16,4 +16,4 @@
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000059

30
OUTPUT/fibonacci_mem_dump.dat
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@ -2,18 +2,18 @@
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000 00000000
00000000 00000001
00000000 00000001
00000000 00000002
00000000 00000003
00000000 00000005
00000000 00000008
00000000 0000000d
00000000 00000015
00000000 00000022
00000000 00000037
00000000 00000059
00000000 00000090
00000000 000000e9
00000000 00000179
00000000 00000262

12
TESTBENCH/da_vinci_tb.v
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@ -62,7 +62,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating fibonacci.dat\n", ""); $write("===> Done simulating fibonacci.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01000000, 'h0100000f); $writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00040000, 'h0004000f);
/* END : test 1*/ /* END : test 1*/
end end
@ -78,7 +78,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating RevFib.dat\n", ""); $write("===> Done simulating RevFib.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff0, 'h03ffffff); $writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 'h0f, `INIT_STACK_POINTER);
/* END : test 2*/ /* END : test 2*/
end end
@ -94,7 +94,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating CS147_SP17_HW01_02.dat\n", ""); $write("===> Done simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h0100800A); $writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h0004800A);
/* END : test 3*/ /* END : test 3*/
end end
@ -110,7 +110,7 @@ begin
#6000 $write("\n"); #6000 $write("\n");
$write("===> Done simulating CS147_FL15_HW01_02.dat\n", ""); $write("===> Done simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff6, 'h03ffffff); $writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 9, `INIT_STACK_POINTER);
/* END : test 4*/ /* END : test 4*/
end end
@ -126,8 +126,8 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating CS147_SP15_HW01_02.dat\n", ""); $write("===> Done simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h01008005); $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048005);
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffffA, 'h03ffffff); $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
/* END : test 5*/ /* END : test 5*/
end end
$stop; $stop;

44
TESTPROGRAM/CS147_FL15_HW01_02.dat
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@ -1,7 +1,7 @@
// ------ Program Part ---- // ------ Program Part ----
@0001000 @0001000
2021000A // addi r1, r1, 0xA; 2021000A // addi r1, r1, 0xA;
20421008 // addi r2, r2, 0x1008; 20420048 // addi r2, r2, 0x0048;
00401301 // sll r2, r2, 0xC; 00401301 // sll r2, r2, 0xC;
00411820 // add r3, r2, r1; 00411820 // add r3, r2, r1;
3C848000 // lui r4, r4, 0x8000; 3C848000 // lui r4, r4, 0x8000;
@ -21,25 +21,25 @@
// ------ Data Part ---- // ------ Data Part ----
@01008000 @00048000
005 // 01008000 005 // 0004 8000
008 // 01008001 008 // 0004 8001
009 // 01008002 009 // 0004 8002
010 // 01008003 010 // 0004 8003
020 // 01008004 020 // 0004 8004
029 // 01008005 029 // 0004 8005
02D // 01008006 02D // 0004 8006
02F // 01008007 02F // 0004 8007
032 // 01008008 032 // 0004 8008
037 // 01008009 037 // 0004 8009
002 // 0100800A 002 // 0004 800A
004 // 0100800B 004 // 0004 800B
008 // 0100800C 008 // 0004 800C
010 // 0100800D 010 // 0004 800D
020 // 0100800E 020 // 0004 800E
040 // 0100800F 040 // 0004 800F
080 // 01008010 080 // 0004 8010
100 // 01008011 100 // 0004 8011
200 // 01008012 200 // 0004 8012
400 // 01008013 400 // 0004 8013

2
TESTPROGRAM/CS147_SP15_HW01_02.dat
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@ -2,7 +2,7 @@
20000001 // addi r0, r0, 0x1; 20000001 // addi r0, r0, 0x1;
20210002 // addi r1, r1, 0x2; 20210002 // addi r1, r1, 0x2;
20420000 // addi r2, r2, 0x0; 20420000 // addi r2, r2, 0x0;
3C630100 // lui r3, 0x100; 3C630004 // lui r3, 0x0004;
34638000 // ori r3, r3, 0x8000; 34638000 // ori r3, r3, 0x8000;
20840005 // addi r4, r4, 0x5; 20840005 // addi r4, r4, 0x5;
00010020 // LOOP: add r0, r0, r1; 00010020 // LOOP: add r0, r0, r1;

24
TESTPROGRAM/CS147_SP17_HW01_02.dat
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@ -1,6 +1,6 @@
// ------ Program Part ---- // ------ Program Part ----
@0001000 @0001000
20001008 // addi r0, r0, 0x1008 20000048 // addi r0, r0, 0x0048
00000301 // sll r0, r0, 0xC 00000301 // sll r0, r0, 0xC
20420009 // addi r2, r2, 0x9 20420009 // addi r2, r2, 0x9
10410007 // LOOP: beq r1, r2, END 10410007 // LOOP: beq r1, r2, END
@ -14,15 +14,15 @@ AC050000 // sw r5, r0, 0x0
AC050000 // END: sw r5, r0, 0x0 AC050000 // END: sw r5, r0, 0x0
// ------ Data Part ---- // ------ Data Part ----
@01008000 @00048000
0A // 0100 8000 0A // 0004 8000
0B // 0100 8001 0B // 0004 8001
0C // 0100 8002 0C // 0004 8002
0D // 0100 8003 0D // 0004 8003
0E // 0100 8004 0E // 0004 8004
0F // 0100 8005 0F // 0004 8005
10 // 0100 8006 10 // 0004 8006
11 // 0100 8007 11 // 0004 8007
12 // 0100 8008 12 // 0004 8008
13 // 0100 8008 13 // 0004 8008

2
TESTPROGRAM/fibonacci.dat
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@ -1,6 +1,6 @@
@0001000 @0001000
20420001 // addi r2, r2, 0x0001; 20420001 // addi r2, r2, 0x0001;
3C000100 // lui r0, 0x0100; 3C000004 // lui r0, 0x0004;
AC010000 // sw r1, r0, 0x0000; AC010000 // sw r1, r0, 0x0000;
20000001 // loop: addi r0, r0, 0x0001; 20000001 // loop: addi r0, r0, 0x0001;
AC020000 // sw r2, r0, 0x0000; AC020000 // sw r2, r0, 0x0000;

9
control_unit.v
View File

@ -171,6 +171,8 @@ endtask
reg read, write; reg read, write;
buf (READ, read); buf (READ, read);
buf (WRITE, write); buf (WRITE, write);
//assign READ = read;
//assign WRITE = write;
reg [31:0] C; reg [31:0] C;
@ -313,13 +315,18 @@ always @ (state) begin
// wd_sel_3 - pc_inc or wd_sel_2 // wd_sel_3 - pc_inc or wd_sel_2
// jal - pc_inc, else wd_sel_2 // jal - pc_inc, else wd_sel_2
C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1; C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1;
// ma_sel_1 - alu_out for lw or sw, sp for push or pop
C[`ma_sel_1] = opcode == `OP_LW || opcode == `OP_SW ? 1'b0 : 1'b1;
// ma_sel_2 - 1 for pc, 0 for everything else
C[`ma_sel_2] = opcode == `OP_LW || opcode == `OP_SW || opcode == `OP_PUSH || opcode == `OP_POP ? 1'b0 : 1'b1;
// md_sel_1 - r1 for push, r2 for sw // md_sel_1 - r1 for push, r2 for sw
C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0; C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0;
end end
`PROC_MEM: begin `PROC_MEM: begin
// load now // load now
// push or sw - write to memory // push or sw - write to memory
if (opcode == 6'h1b || opcode == 6'h2b) begin if (opcode == `OP_PUSH || opcode == `OP_SW) begin
read = 1'b0; read = 1'b0;
write = 1'b1; write = 1'b1;
end end

4
prj_definition.v
View File

@ -23,7 +23,7 @@
`define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1) `define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1)
`define ADDRESS_WIDTH 26 `define ADDRESS_WIDTH 26
`define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1) `define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1)
`define MEM_SIZE (2 ** `ADDRESS_WIDTH) `define MEM_SIZE (2 ** (`ADDRESS_WIDTH - 6))
`define MEM_INDEX_LIMIT (`MEM_SIZE - 1) `define MEM_INDEX_LIMIT (`MEM_SIZE - 1)
`define NUM_OF_REG 32 `define NUM_OF_REG 32
`define REG_INDEX_LIMIT (`NUM_OF_REG -1) `define REG_INDEX_LIMIT (`NUM_OF_REG -1)
@ -41,4 +41,4 @@
// define ISA parameters // define ISA parameters
`define INST_START_ADDR 32'h00001000 `define INST_START_ADDR 32'h00001000
`define INIT_STACK_POINTER 32'h03ffffff `define INIT_STACK_POINTER 32'h000fffff