406 lines
14 KiB
Verilog
406 lines
14 KiB
Verilog
// Name: control_unit.v
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// Module: CONTROL_UNIT
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// Output: CTRL : Control signal for data path
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// READ : Memory read signal
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// WRITE : Memory Write signal
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//
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// Input: ZERO : Zero status from ALU
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// CLK : Clock signal
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// RST : Reset Signal
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//
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// Notes: - Control unit synchronize operations of a processor
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// Assign each bit of control signal to control one part of data path
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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// Control signals, same as in data_path.v
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`define pc_load 0
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`define pc_sel_1 1
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`define pc_sel_2 2
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`define pc_sel_3 3
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`define ir_load 4
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`define r1_sel_1 5
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`define reg_r 6
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`define reg_w 7
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`define sp_load 8
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`define op1_sel_1 9
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`define op2_sel_1 10
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`define op2_sel_2 11
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`define op2_sel_3 12
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`define op2_sel_4 13
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`define alu_oprn 19:14
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`define ma_sel_1 20
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`define ma_sel_2 21
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`define md_sel_1 22
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`define wd_sel_1 23
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`define wd_sel_2 24
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`define wd_sel_3 25
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`define wa_sel_1 26
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`define wa_sel_2 27
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`define wa_sel_3 28
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// ALU operation codes
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`define ALU_NOP 6'h00
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`define ALU_ADD 6'h01
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`define ALU_SUB 6'h02
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`define ALU_MUL 6'h03
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`define ALU_SRL 6'h04
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`define ALU_SLL 6'h05
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`define ALU_AND 6'h06
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`define ALU_OR 6'h07
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`define ALU_NOR 6'h08
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`define ALU_SLT 6'h09
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// Instruction opcodes
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// R-type
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`define OP_RTYPE 6'h00
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`define FN_ADD 6'h20
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`define FN_SUB 6'h22
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`define FN_MUL 6'h2c
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`define FN_AND 6'h24
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`define FN_OR 6'h25
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`define FN_NOR 6'h27
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`define FN_SLT 6'h2a
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`define FN_SLL 6'h01
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`define FN_SRL 6'h02
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`define FN_JR 6'h08
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// I-type
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`define OP_ADDI 6'h08
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`define OP_MULI 6'h1d
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`define OP_ANDI 6'h0c
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`define OP_ORI 6'h0d
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`define OP_LUI 6'h0f
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`define OP_SLTI 6'h0a
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`define OP_BEQ 6'h04
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`define OP_BNE 6'h05
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`define OP_LW 6'h23
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`define OP_SW 6'h2b
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// J-type
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`define OP_JMP 6'h02
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`define OP_JAL 6'h03
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`define OP_PUSH 6'h1b
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`define OP_POP 6'h1c
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module CONTROL_UNIT(CTRL, READ, WRITE, ZERO, INSTRUCTION, CLK, RST);
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// Output signals
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output [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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output READ, WRITE;
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// input signals
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input ZERO, CLK, RST;
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input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
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task print_instruction;
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input [`DATA_INDEX_LIMIT:0] inst;
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reg [5:0] opcode2;
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reg [4:0] rs2;
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reg [4:0] rt2;
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reg [4:0] rd2;
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reg [4:0] shamt2;
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reg [5:0] funct2;
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reg [15:0] immediate2;
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reg [25:0] address2;
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begin
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// parse the instruction
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// R-type
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{opcode2, rs2, rt2, rd2, shamt2, funct2} = inst;
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// I-type
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{opcode2, rs2, rt2, immediate2 } = inst;
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// J-type
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{opcode2, address2} = inst;
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$write("@ %6dns -> [0X%08h] ", $time, inst);
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case(opcode2)
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// R-Type
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6'h00 : begin
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case(funct2)
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6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
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6'h01: $write("sll r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
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6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
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6'h08: $write("jr r[%02d];", rs2);
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default: $write("");
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endcase
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end
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// I-type
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6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h0f : $write("lui r[%02d], 0X%04h;", rt2, immediate2);
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6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
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// J-Type
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6'h02 : $write("jmp 0X%07h;", address2);
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6'h03 : $write("jal 0X%07h;", address2);
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6'h1b : $write("push;");
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6'h1c : $write("pop;");
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default: $write("");
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endcase
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$write("\n");
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end
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endtask
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//------------------------------------- END ---------------------------------------//
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reg read, write;
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buf (READ, read);
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buf (WRITE, write);
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//assign READ = read;
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//assign WRITE = write;
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reg [31:0] C;
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buf ctrl_buf [31:0] (CTRL, C);
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// Parse the instruction data
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reg [5:0] opcode;
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reg [4:0] rs;
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reg [4:0] rt;
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reg [4:0] rd;
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reg [4:0] shamt;
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reg [5:0] funct;
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reg [15:0] imm;
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reg [25:0] addr;
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// State machine
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wire [2:0] state;
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PROC_SM proc_sm(state, CLK, RST);
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// TBD - take action on each +ve edge of clock
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always @ (state) begin
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// R-type
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{opcode, rs, rt, rd, shamt, funct} = INSTRUCTION;
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// I-type
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{opcode, rs, rt, imm} = INSTRUCTION;
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// J-type
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{opcode, addr} = INSTRUCTION;
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// Print current state
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// $write("@ %6dns -> ", $time);
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// $write("STATE ", state, ": ");
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// case (state)
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// `PROC_FETCH: $write("FETCH");
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// `PROC_DECODE: $write("DECODE");
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// `PROC_EXE: $write("EXECUTE");
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// `PROC_MEM: $write("MEMORY");
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// `PROC_WB: $write("WRITE BACK");
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// default: $write("INVALID");
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// endcase
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// $write("\n");
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case (state)
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// fetch - next instruction from memory at PC
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`PROC_FETCH: begin
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// set everything in ctrl to 0
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C = 32'b0;
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// memory
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read = 1'b1;
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write = 1'b0;
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// selections
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C[`ma_sel_2] = 1'b1; // load data from mem[PC]
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end
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// decode - parse instruction and read values from register file
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`PROC_DECODE: begin
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// loaded in previous state, set to 0
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read = 1'b0;
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// load now
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C[`ir_load] = 1'b1;
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C[`reg_r] = 1'b1;
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end
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// execute - perform operation based on instruction
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`PROC_EXE: begin
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print_instruction(INSTRUCTION);
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// loaded in previous state, set to 0
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C[`ir_load] = 1'b0;
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// selections
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// r1_sel_1: push - store value of r0 at stack pointer
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C[`r1_sel_1] = opcode != 6'h1b ? 1'b0 : 1'b1;
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// wa_sel_1: R-type - write to rd, I-type - write to rt
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C[`wa_sel_1] = opcode == 6'h00 ? 1'b0 : 1'b1;
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// wa_sel_2: jal - write to r31, pop - write to r0
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C[`wa_sel_2] = opcode == 6'h03 ? 1'b1 : 1'b0;
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// wa_sel_3: push or pop - wa_sel_2, else wa_sel_1
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C[`wa_sel_3] = opcode == 6'h03 || opcode == 6'h1c ? 1'b0 : 1'b1;
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// jr - jump to address in register
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C[`pc_sel_1] = opcode == 6'h00 && funct == 6'h08 ? 1'b0 : 1'b1;
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// beq, bne - branch if equal or not equal
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// TODO: this should only be selected if the condition is met
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// pc_sel_2 = opcode == 6'h04 || opcode == 6'h05 ? 1'b1 : 1'b0;
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// jmp, jal - jump to address
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C[`pc_sel_3] = opcode == `OP_JMP || opcode == `OP_JAL ? 1'b0 : 1'b1;
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// alu_oprn - operation to be performed by ALU
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// R-type
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if (opcode == `OP_RTYPE) begin
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case (funct)
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`FN_ADD: C[`alu_oprn] = `ALU_ADD;
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`FN_SUB: C[`alu_oprn] = `ALU_SUB;
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`FN_MUL: C[`alu_oprn] = `ALU_MUL;
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`FN_SRL: C[`alu_oprn] = `ALU_SRL;
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`FN_SLL: C[`alu_oprn] = `ALU_SLL;
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`FN_AND: C[`alu_oprn] = `ALU_AND;
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`FN_OR: C[`alu_oprn] = `ALU_OR;
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`FN_NOR: C[`alu_oprn] = `ALU_NOR;
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`FN_SLT: C[`alu_oprn] = `ALU_SLT;
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// I-type and J-type
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else begin
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case (opcode)
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// I-type
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`OP_ADDI: C[`alu_oprn] = `ALU_ADD; // addi
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`OP_MULI: C[`alu_oprn] = `ALU_MUL; // muli
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`OP_ANDI: C[`alu_oprn] = `ALU_AND; // andi
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`OP_ORI: C[`alu_oprn] = `ALU_OR; // ori
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`OP_SLTI: C[`alu_oprn] = `ALU_SLT; // slti
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`OP_BEQ: C[`alu_oprn] = `ALU_SUB; // beq - sub
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`OP_BNE: C[`alu_oprn] = `ALU_SUB; // bne - sub
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`OP_LW: C[`alu_oprn] = `ALU_ADD; // lw - add
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`OP_SW: C[`alu_oprn] = `ALU_ADD; // sw - add
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// J-type
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`OP_PUSH: C[`alu_oprn] = `ALU_SUB; // push - sub
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`OP_POP: C[`alu_oprn] = `ALU_ADD; // pop - add
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default: C[`alu_oprn] = `ALU_NOP;
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endcase
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end
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// op1_sel_1 - select r1 or sp based on opcode
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// push or pop - sp, else r1
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C[`op1_sel_1] = opcode == 6'h1b || opcode == 6'h1c ? 1'b1 : 1'b0;
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// op2_sel_1 - select 1 or shamt based on alu_oprn
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// sll or srl - shamt, else 1 (for increments/decrements)
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C[`op2_sel_1] = C[`alu_oprn] == 6'h04 || C[`alu_oprn] == 6'h05 ? 1'b1 : 1'b0;
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// op2_sel_2 - select imm_zx or imm_sx based on alu_oprn
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// logical (and, or) - imm_zx, else imm_sx; ('nor' not availble in I-type)
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C[`op2_sel_2] = C[`alu_oprn] == 6'h06 || C[`alu_oprn] == 6'h07 ? 1'b0 : 1'b1;
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// op2_sel_3 - select op2_sel_2 or op2_sel_1 based on alu_oprn
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// R-type - op2_sel_1, I-type - op2_sel_2
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C[`op2_sel_3] = opcode == 6'h00 ? 1'b1 : 1'b0;
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// op2_sel_4 - select op2_sel_3 or r2
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// I-type or shift or inc/dec - op2_sel_3, else r2
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// i.e. r2 only if R-type and not shift
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C[`op2_sel_4] = opcode != 6'h00 || C[`alu_oprn] == 6'h04 || C[`alu_oprn] == 6'h05 ? 1'b0 : 1'b1;
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// wd_sel_1 - alu_out or DATA_IN
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C[`wd_sel_1] = 1'b0;
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// wd_sel_2 - wd_sel_1 or imm_zx_lsb
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// lui - imm_zx_lsb, else wd_sel_1
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C[`wd_sel_2] = opcode == 6'h0f ? 1'b1 : 1'b0;
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// wd_sel_3 - pc_inc or wd_sel_2
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// jal - pc_inc, else wd_sel_2
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C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1;
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// ma_sel_1 - alu_out for lw or sw, sp for push or pop
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C[`ma_sel_1] = opcode == `OP_LW || opcode == `OP_SW ? 1'b0 : 1'b1;
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// ma_sel_2 - 1 for pc, 0 for everything else
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C[`ma_sel_2] = opcode == `OP_LW || opcode == `OP_SW || opcode == `OP_PUSH || opcode == `OP_POP ? 1'b0 : 1'b1;
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// md_sel_1 - r1 for push, r2 for sw
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C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0;
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end
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`PROC_MEM: begin
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// load now
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// push or sw - write to memory
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if (opcode == `OP_PUSH || opcode == `OP_SW) begin
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read = 1'b0;
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write = 1'b1;
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end
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else begin
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// read = 1'b1;
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// write = 1'b0;
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end
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end
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`PROC_WB: begin
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// loaded in previous state, set to 0
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read = 1'b0;
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write = 1'b0;
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// load now
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C[`pc_load] = 1'b1;
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// write to register file if
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// R-type (except jr) or I-type (except beq, bne, sw) or pop or jal
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C[`reg_w] = (opcode == 6'h00 && funct != 6'h08) // R-type (except jr)
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|| (opcode == 6'h08 || opcode == 6'h1d || opcode == 6'h0c || opcode == 6'h0d
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|| opcode == 6'h0f || opcode == 6'h0a || opcode == 6'h23) // I-type (except beq, bne, sw)
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|| (opcode == 6'h1c || opcode == 6'h03) // pop or jal
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? 1'b1 : 1'b0;
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// selections
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// pc_sel_2 - branch if equal or not equal
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C[`pc_sel_2] = (opcode == 6'h04 && ZERO) || (opcode == 6'h05 && ~ZERO) ? 1'b1 : 1'b0;
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end
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endcase
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end
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endmodule
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//------------------------------------------------------------------------------------------
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// Module: PROC_SM
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// Output: STATE : State of the processor
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//
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// Input: CLK : Clock signal
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// RST : Reset signal
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//
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// INOUT: MEM_DATA : Data to be read in from or write to the memory
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//
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// Notes: - Processor continuously cycle witnin fetch, decode, execute,
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// memory, write back state. State values are in the prj_definition.v
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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module PROC_SM(STATE,CLK,RST);
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// list of inputs
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input CLK, RST;
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// list of outputs
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output [2:0] STATE;
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reg [2:0] state_sel = 3'bxxx;
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always @ (negedge RST) begin
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// set to invalid value, so that it defaults to fetch
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state_sel = 3'bxxx;
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end
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// TBD - take action on each +ve edge of clock
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always @ (posedge CLK) begin
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case (state_sel)
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`PROC_FETCH: state_sel = `PROC_DECODE;
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`PROC_DECODE: state_sel = `PROC_EXE;
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`PROC_EXE: state_sel = `PROC_MEM;
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`PROC_MEM: state_sel = `PROC_WB;
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`PROC_WB: state_sel = `PROC_FETCH;
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default: state_sel = `PROC_FETCH;
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endcase
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end
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assign STATE = state_sel;
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endmodule
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