2 Commits

Author	SHA1	Message	Date
Yuri Tatishchev	3091103f81	lab-07: gate level model for 32-bit register ... Gate level implementation for the following components: - SR_LATCH - D_LATCH - D_FF - REG1 - REG32	2024-10-19 18:39:30 -07:00
Iurii Tatishchev	5520d6d716	initial commit	2024-10-01 10:39:56 -07:00