(WIP): D Latch and D FlipFlop
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11
logic.v
11
logic.v
@ -69,7 +69,11 @@ input D, C;
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input nP, nR;
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input nP, nR;
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output Q,Qbar;
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output Q,Qbar;
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// TBD
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wire Cbar, Y, Ybar;
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not C_inv(Cbar, C);
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D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
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SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
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endmodule
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endmodule
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@ -82,7 +86,10 @@ input D, C;
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input nP, nR;
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input nP, nR;
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output Q,Qbar;
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output Q,Qbar;
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// TBD
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wire Dbar;
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not D_inv(Dbar, D);
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SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
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endmodule
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endmodule
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