From 7c0645eaa1b6635d11782cc9ae6ca194ea7b8e2e Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Sat, 19 Oct 2024 15:47:35 -0700 Subject: [PATCH] (WIP): D Latch and D FlipFlop --- logic.v | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/logic.v b/logic.v index a575ad1..6c9b251 100644 --- a/logic.v +++ b/logic.v @@ -69,7 +69,11 @@ input D, C; input nP, nR; output Q,Qbar; -// TBD +wire Cbar, Y, Ybar; +not C_inv(Cbar, C); +D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR); + +SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR); endmodule @@ -82,7 +86,10 @@ input D, C; input nP, nR; output Q,Qbar; -// TBD +wire Dbar; +not D_inv(Dbar, D); + +SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR); endmodule