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Iurii Tatishchev
2024-10-01 10:39:56 -07:00
commit 5520d6d716
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85
TESTBENCH/alu_tb.v Normal file
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// Name: alu_tb.v
// Module: ALU_TB
//
// Notes: - Testbench for ALU
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module ALU_TB;
// reg list
reg [`DATA_INDEX_LIMIT:0] OP1; // operand 1
reg [`DATA_INDEX_LIMIT:0] OP2; // operand 2
reg [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
// output list
wire [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
wire ZERO;
// results
integer ridx;
reg [`DATA_INDEX_LIMIT:0] result[199:0];
// Testcases
integer oprnd_idx, oprn_idx;
integer NumSet01[0:7];
integer NumSet02[0:7];
integer OpCode[0:8];
ALU alu_inst(.OUT(OUT), .ZERO(ZERO), .OP1(OP1), .OP2(OP2), .OPRN(OPRN));
initial
begin
// Initialize number sets
NumSet01[0] = 10; NumSet01[1] = -15; NumSet01[2] = 25; NumSet01[3] = -30; NumSet01[4] = 0; NumSet01[5] = -15; NumSet01[6] = 23; NumSet01[7] = 0;
NumSet02[0] = 10; NumSet02[1] = 15; NumSet02[2] = -25; NumSet02[3] = -30; NumSet02[4] = 0; NumSet02[5] = 42; NumSet02[6] = 0; NumSet02[7] = 70;
ridx = 0;
// Set of operation
OpCode[0] = 1; // add
OpCode[1] = 2; // sub
OpCode[2] = 3; // mult
OpCode[3] = 4; // shiftR
OpCode[4] = 5; // shiftL
OpCode[5] = 6; // and
OpCode[6] = 7; // or
OpCode[7] = 8; // nor
OpCode[8] = 9; // slt
// Loop through operands and operation
for(oprnd_idx=0; oprnd_idx<8; oprnd_idx=oprnd_idx+1)
begin
for(oprn_idx=0; oprn_idx<9; oprn_idx=oprn_idx+1)
begin
#1 OP1=NumSet01[oprnd_idx]; OP2=NumSet02[oprnd_idx]; OPRN=OpCode[oprn_idx];
#1
$write("===> %0d ",$signed(OP1));
case(OPRN)
1: $write("+");
2: $write("-");
3: $write("*");
4: $write(">>");
5: $write("<<");
6: $write("&");
7: $write("|");
8: $write("|~");
9: $write("slt");
endcase
$write(" %0d = %0d [%d]\n", $signed(OP2), $signed(OUT), ZERO);
result[ridx] = OUT; ridx = ridx + 1;
result[ridx] = ZERO; ridx = ridx + 1;
end
end
#1
$writememh("./OUTPUT/alu_tb.out", result, 0, (ridx-1));
$stop;
end
endmodule

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TESTBENCH/barrel_shifter_tb.v Normal file
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// Name: barrel_shifter_tb.v
// Module: BARREL_SHIFTER32_TB
//
// Notes: - Testbench for shift module
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module BARREL_SHIFTER32_TB;
reg [31:0] D;
reg [31:0] S;
reg LnR;
wire [31:0] Y;
integer reg_idx;
reg [`DATA_INDEX_LIMIT:0] result[0:63];
integer i, e;
integer no_of_test=0;
integer no_of_pass=0;
SHIFT32 shift_inst(.Y(Y), .D(D), .S(S), .LnR(LnR));
initial
begin
reg_idx=0;
D=32'ha5a5a5a5;
S=32'h00000000;
LnR=1'b1; // left shift
for(i=1; i<33; i=i+1)
begin
#5
no_of_test = no_of_test + 1;
S=i;
e = D << S;
#5
if (e !== Y)
begin
$write("[TEST %2d] (%8x << %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
end
else
no_of_pass = no_of_pass + 1;
result[reg_idx] = Y; reg_idx=reg_idx+1;
end
#5 LnR=1'b0; // right shift
for(i=1; i<33; i=i+1)
begin
#5
no_of_test = no_of_test + 1;
S=i;
e = D >> S;
#5
if (e !== Y)
begin
$write("[TEST %2d] (%8x >> %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
end
else
no_of_pass = no_of_pass + 1;
result[reg_idx] = Y; reg_idx=reg_idx+1;
end
$write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/barret_shifter_tb.out",result);
$stop;
end
endmodule

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// Name: da_vinci_tb.v
// Module: DA_VINCI_TB
//
// Outputs are for testbench observations only
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for DA_VINCI system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module DA_VINCI_TB;
// output list
wire [`ADDRESS_INDEX_LIMIT:0] ADDR;
wire READ, WRITE, CLK;
// inout list
wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
// reset
reg RST;
integer t1=1, t2=1, t3=1, t4=1, t5=1;
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// DA_VINCI v1.0 instance
defparam da_vinci_inst.mem_init_file = "./TESTPROGRAM/fibonacci.dat";
//defparam da_vinci_inst.mem_init_file = "RevFib.dat";
DA_VINCI da_vinci_inst(.MEM_DATA_OUT(MEM_DATA_OUT),
.MEM_DATA_IN(MEM_DATA_IN),
.ADDR(ADDR), .READ(READ),
.WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
RST=1'b1;
if (t1 === 1)
begin
/* START : test 1*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating fibonacci.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/fibonacci.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating fibonacci.dat\n", "");
$write("\n");
$writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01000000, 'h0100000f);
/* END : test 1*/
end
if (t2 === 1)
begin
/* START : test 2*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating RevFib.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/RevFib.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating RevFib.dat\n", "");
$write("\n");
$writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff0, 'h03ffffff);
/* END : test 2*/
end
if (t3 === 1)
begin
/* START : test 3*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_SP17_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h0100800A);
/* END : test 3*/
end
if (t4 === 1)
begin
/* START : test 4*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_FL15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#6000 $write("\n");
$write("===> Done simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff6, 'h03ffffff);
/* END : test 4*/
end
if (t5 === 1)
begin
/* START : test 5*/
#5 RST=1'b0;
#5 RST=1'b1;
$write("\n");
$write("===> Simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n");
$readmemh("./TESTPROGRAM/CS147_SP15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
#5000 $write("\n");
$write("===> Done simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n");
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h01008005);
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffffA, 'h03ffffff);
/* END : test 5*/
end
$stop;
end
endmodule;

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// Name: full_adder_tb.v
// Module: FULL_ADDER_TB
//
// Notes: - Testbench for full adder
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module FULL_ADDER_TB;
reg A, B, CI;
wire S, CO;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
integer i;
FULL_ADDER fa_inst(.S(S), .CO(CO), .A(A), .B(B), .CI(CI));
initial
begin
A=0; B=0; CI=0;
#1 result[0] = 32'h00000000 | {CO,S};
for(i=1; i<8; i=i+1)
begin
#1 CI=i[2]; A=i[1]; B=i[0];
#1 result[i] = 32'h00000000 | {CO,S};
end
#1
$writememh("./OUTPUT/full_adder.out",result);
$stop;
end
endmodule

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TESTBENCH/half_adder_tb.v Normal file
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// Name: half_adder_tb.v
// Module: HALF_ADDER_TB
//
// Notes: - Testbench for half adder
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module HALF_ADDER_TB;
reg A, B;
wire Y, C;
reg [`DATA_INDEX_LIMIT:0] results[0:3];
HALF_ADDER ha_inst(.Y(Y), .C(C), .A(A), .B(B));
initial
begin
A=1'b0; B=1'b0;
#1 results[0] = 32'h00000000 | {C,Y};
#1 A=1'b0; B=1'b1;
#1 results[1] = 32'h00000000 | {C,Y};
#1 A=1'b1; B=1'b0;
#1 results[2] = 32'h00000000 | {C,Y};
#1 A=1'b1; B=1'b1;
#1 results[3] = 32'h00000000 | {C,Y};
#5
$writememh("./OUTPUT/half_adder.out",results,0,3);
$stop;
end
endmodule

144
TESTBENCH/logic_32_bit_tb.v Normal file
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// Name: logic_32_bit_tb.v
// Module: NOR32_2x1_TB
// AND32_2x1_TB
// INV32_1x1_TB
// OR32_2x1_TB
//
// Notes: - Testbench for shift module
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module NOR32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
NOR32_2x1 nor32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/NOR32_2x1_TB.out",result);
$stop;
end
endmodule
module AND32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
AND32_2x1 and32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/AND32_2x1_TB.out",result);
$stop;
end
endmodule
module INV32_1x1_TB;
//Driver
reg [31:0] A;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
INV32_1x1 inv32_1x1_inst(.Y(Y), .A(A));
initial
begin
i=0;
A=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; // Y=32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; // Y = 32'h5A5A5A5A
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/INV32_1x1_TB.out",result);
$stop;
end
endmodule
module OR32_2x1_TB;
//Driver
reg [31:0] A, B;
// Obsrver
wire [31:0] Y;
// result
integer i;
reg [31:0] result [0:4];
OR32_2x1 or32_2x1_inst(.Y(Y), .A(A), .B(B));
initial
begin
i=0;
A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
#1 result[i] = Y; i=i+1;
#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'hFFFFFFFF
#1 result[i] = Y; i=i+1;
#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
#1 result[i] = Y; i=i+1;
#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/OR32_2x1_TB.out",result);
$stop;
end
endmodule

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// Name: logic_tb.v
// Module: TWOSCOMP32_TB,
// TWOSCOMP64_TB,
// SR_LATCH_TB,
// D_LATCH_TB,
// D_FF_PE_TB,
// REG1_TB,
// REG32_TB,
// DECODER_5x32_TB
//
// Notes: - Testbench for multiplier
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module DECODER_5x32_TB;
// observer
wire [31:0] D;
// driver
reg [4:0] I;
// result
integer i, idx;
reg [31:0] result[0:31];
DECODER_5x32 decoder_5x32_inst0(.D(D),.I(I));
initial
begin
i=0;
for(idx=0; idx<32; idx = idx + 1)
begin
#1 I=idx;
#1 result[i] = D; i=i+1;
end
#1
$writememb("./OUTPUT/decoder_5x32_tb.out",result);
$stop;
end
endmodule
module REG32_TB;
//driver
reg [`DATA_INDEX_LIMIT:0] D;
reg LOAD, RESET;
// oberver
wire [`DATA_INDEX_LIMIT:0] Q;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
REG32 reg32_inst(.Q(Q), .CLK(clk), .LOAD(LOAD), .D(D), .RESET(RESET));
initial
begin
i=0; RESET=1; D=32'ha5a5a5a5; LOAD=0;
// Reset
#1 D=32'ha5a5a5a5; LOAD=0; RESET=0;
#1 result[i] = Q; i=i+1;
// Hold
#1 D=32'ha5a5a5a5; LOAD=0; RESET=1;
#1 result[i] = Q; i=i+1;
// Normal operation
#6 D=32'ha5a5a5a5; LOAD=1; RESET=1;
#5 result[i] = Q; i=i+1;
#5 D=32'hffff0000; LOAD=1; RESET=1;
#5 result[i] = Q; i=i+1;
// Reset
#1 D=32'h0000ffff; LOAD=1; RESET=0;
#1 result[i] = Q; i=i+1;
// Normal operation
#9 D=32'h0000ffff; LOAD=1; RESET=1;
#1 result[i] = Q; i=i+1;
#10 result[i] = Q; i=i+1;
#10 D=32'h5a5a5a5a; LOAD=0; RESET=1;
#10
result[i] = Q; i=i+1;
$writememh("./OUTPUT/d_reg32_tb.out",result);
$stop;
end
endmodule
module REG1_TB;
//driver
reg D, L, nP, nR;
// oberver
wire Q,Qbar;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:6];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
REG1 reg1_inst(.Q(Q), .Qbar(Qbar), .C(clk),
.L(L), .D(D), .nP(nP), .nR(nR));
initial
begin
i=0; nP=1; nR=1; D=0; L=0;
// Preset
#1 D=0; L=0; nP=0; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Hold
#1 D=0; L=0; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Normal operation
#6 D=0; L=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#5 D=1; L=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Reset
#1 D=1; L=1; nP=1; nR=0;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
// Normal operation
#9 D=1; L=1; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
#10 D=0; L=0; nP=1; nR=1;
#10
result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
$writememh("./OUTPUT/d_reg1_tb.out",result);
$stop;
end
endmodule
module D_FF_TB;
//driver
reg D, nP, nR;
// oberver
wire Q,Qbar;
// clock
wire clk;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:6];
CLK_GENERATOR clk_gen_inst(.CLK(clk));
D_FF d_ff_inst(.Q(Q), .Qbar(Qbar), .C(clk),
.D(D), .nP(nP), .nR(nR));
initial
begin
i=0; nP=1; nR=1; D=0;
// Preset
#1 D=0; nP=0; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Hold
#1 D=0; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Normal operation
#6 D=0; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#5 D=1; nP=1; nR=1;
#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Reset
#1 D=1; nP=1; nR=0;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
// Normal operation
#9 D=1; nP=1; nR=1;
#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
#10
result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
$writememh("./OUTPUT/d_ff_tb.out",result);
$stop;
end
endmodule
module D_LATCH_TB;
// driver
reg D, C, nP, nR;
// oberver
wire Q,Qbar;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:7];
D_LATCH d_latch_inst(.Q(Q), .Qbar(Qbar), .D(D),
.C(C), .nP(nP), .nR(nR));
initial
begin
i=0;
// Normal preset
#1 C=0; D=0; nR=1; nP=0; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Hold 1 on C=0
#1 C=0; D=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1 C=0; D=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Normal reset
#1 C=0; D=0; nR=0; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Hold 0 on C=0
#1 C=0; D=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1 C=0; D=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Set on clock
#1 C=1; D=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
// Reset on clock
#1 C=1; D=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
#1
$writememh("./OUTPUT/d_latch_tb.out",result);
$stop;
end
endmodule
module SR_LATCH_TB;
// driver
reg S, R, C, nP, nR;
// oberver
wire Q,Qbar;
// Result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:13];
SR_LATCH sr_latch_inst(.Q(Q), .Qbar(Qbar), .S(S),
.R(R), .C(C), .nP(nP), .nR(nR));
initial
begin
i=0;
// Normal reset preset
#1 C=0; S=0; R=0; nR=1; nP=0; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold 1 on C=0
#1 C=0; S=0; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=0; R=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=1; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Normal reset
#1 C=0; S=0; R=0; nR=0; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold 0 on C=0
#1 C=0; S=0; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=0; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1 C=0; S=1; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Set on clock
#1 C=1; S=1; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold
#1 C=1; S=0; R=0; nR=1; nP=1; // Q=1
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Reset on clock
#1 C=1; S=0; R=1; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
// Hold
#1 C=1; S=0; R=0; nR=1; nP=1; // Q=0
#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
#1
$writememh("./OUTPUT/sr_latch_tb.out",result);
$stop;
end
endmodule
module TWOSCOMP32_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
// wire
wire [`DATA_INDEX_LIMIT:0] Y;
// result
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:1];
TWOSCOMP32 inst_2scomp_01(.Y(Y), .A(A));
initial
begin
i=0;
A = 10;
#1 result[i] = Y; i = i + 1;
#1 A=-5;
#1 result[i] = Y; i = i + 1;
#1
$writememh("./OUTPUT/twoscomp32_tb.out",result);
$stop;
end
endmodule
module TWOSCOMP64_TB;
// driver
reg [`DOUBLE_DATA_INDEX_LIMIT:0] A;
// wire
wire [`DOUBLE_DATA_INDEX_LIMIT:0] Y;
// result
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:1];
TWOSCOMP64 inst_2scomp_01(.Y(Y), .A(A));
initial
begin
i=0;
A = 10;
#1 result[i] = Y; i = i + 1;
#1 A=-5;
#1 result[i] = Y; i = i + 1;
#1
$writememh("./OUTPUT/twoscomp64_tb.out",result);
$stop;
end
endmodule

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// Name: proj_2_tb.v
// Module: DA_VINCI_TB
//
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for MEMORY_64MB memory system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MEM_64MB_TB;
// Storage list
reg [`ADDRESS_INDEX_LIMIT:0] ADDR;
// reset
reg READ, WRITE, RST;
// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;
// wire lists
wire CLK;
wire [`DATA_INDEX_LIMIT:0] DATA;
assign DATA = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} };
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// 64MB memory instance
defparam mem_inst.mem_init_file = "mem_content_01.dat";
MEMORY_64MB mem_inst(.DATA(DATA), .ADDR(ADDR), .READ(READ),
.WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
RST=1'b1;
READ=1'b0;
WRITE=1'b0;
DATA_REG = {`DATA_WIDTH{1'b0} };
no_of_test = 0;
no_of_pass = 0;
load_data = 'h00414020;
// Start the operation
#10 RST=1'b0;
#10 RST=1'b1;
// Write cycle
for(i=1;i<10; i = i + 1)
begin
#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR = i;
end
// Read Cycle
#10 READ=1'b0; WRITE=1'b0;
#5 no_of_test = no_of_test + 1;
if (DATA !== {`DATA_WIDTH{1'bz}})
$write("[TEST] Read %1b, Write %1b, expecting 32'hzzzzzzzz, got %8h [FAILED]\n", READ, WRITE, DATA);
else
no_of_pass = no_of_pass + 1;
// test of write data
for(i=0;i<10; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR = i;
#5 no_of_test = no_of_test + 1;
if (DATA !== i)
$write("[TEST] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", READ, WRITE, i, DATA);
else
no_of_pass = no_of_pass + 1;
end
// test for the initialize data
for(i='h001000; i<'h001010; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR = i;
#5 no_of_test = no_of_test + 1;
if (DATA !== load_data)
$write("[TEST] Read %1b, Write %1b, Addr %7h, expecting %8h, got %8h [FAILED]\n",
READ, WRITE, ADDR, load_data, DATA);
else
no_of_pass = no_of_pass + 1;
load_data = load_data + 1;
end
#10 READ=1'b0; WRITE=1'b0; // No op
#10 $write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/mem_dump_01.dat", mem_inst.sram_32x64m, 'h0000000, 'h000000f);
$writememh("./OUTPUT/mem_dump_02.dat", mem_inst.sram_32x64m, 'h0001000, 'h000100f);
$stop;
end
endmodule;

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// Name: mult_tb.v
// Module: MULT_U_TB, MULT_TB
//
// Notes: - Testbench for multiplier
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MULT_U_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
// outputs to observe
wire [`DATA_INDEX_LIMIT:0] HI, LO;
// result registers
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:4];
MULT32_U mult32_u_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
initial
begin
i=0;
A=10; B=20; // Y = 10 * 20 = 200
#1 result[i] = {HI,LO}; i=i+1;
#1 A=3; B=15; // Y = 3 * 15 = 45
#1 result[i] = {HI,LO}; i=i+1;
#1 A=16; B=7; // Y = 16 * 7 = 112
#1 result[i] = {HI,LO}; i=i+1;
#1 A=10; B=19; // Y = 10 * 19 = 190
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1
$writememh("./OUTPUT/mult32_u_tb.out", result);
$stop;
end
endmodule
module MULT_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
// outputs to observe
wire [`DATA_INDEX_LIMIT:0] HI, LO;
// result registers
integer i;
reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:7];
MULT32 mult32_inst_0(.HI(HI), .LO(LO), .A(A), .B(B));
initial
begin
i=0;
A=10; B=20; // Y = 10 * 20 = 200
#1 result[i] = {HI,LO}; i=i+1;
#1 A=-3; B=-15; // Y = 3 * 15 = 45
#1 result[i] = {HI,LO}; i=i+1;
#1 A=-16; B=7; // Y = 16 * 7 = -112
#1 result[i] = {HI,LO}; i=i+1;
#1 A=10; B=-19; // Y = 10 * 19 = -190
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h90000000; B=32'h70000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h70000000; B=32'h90000000;
#1 result[i] = {HI,LO}; i=i+1;
#1 A=32'h90000000; B=32'h90000000;
#1 result[i] = {HI,LO}; i=i+1;
#1
$writememh("./OUTPUT/mult32_tb.out", result);
$stop;
end
endmodule

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// Name: mux32_tb.v
// Module: MUX32_2x1_TB
// MUX32_16x1_TB
// MUX32_32x1_TB
//
// Notes: - Testbench for different multiplexer
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module MUX32_32x1_TB;
reg [31:0] I [0:31];
reg [4:0] S;
wire [31:0] Y;
integer i;
reg [31:0] result [0:31];
MUX32_32x1 mux_inst_01(.Y(Y),
.I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]),
.I4(I[4]), .I5(I[5]), .I6(I[6]), .I7(I[7]),
.I8(I[8]), .I9(I[9]), .I10(I[10]), .I11(I[11]),
.I12(I[12]), .I13(I[13]), .I14(I[14]), .I15(I[15]),
.I16(I[16]), .I17(I[17]), .I18(I[18]), .I19(I[19]),
.I20(I[20]), .I21(I[21]), .I22(I[22]), .I23(I[23]),
.I24(I[24]), .I25(I[25]), .I26(I[26]), .I27(I[27]),
.I28(I[28]), .I29(I[29]), .I30(I[30]), .I31(I[31]),
.S(S));
initial
begin
for(i=0;i<32;i=i+1)
I[i]=i;
for(i=0;i<32;i=i+1)
begin
#1 S = i;
#1 result[i]=Y;
end
#1
$writememh("./OUTPUT/mux32_32x1_tb.out", result);
$stop;
end
endmodule
module MUX32_16x1_TB;
reg [31:0] I [0:15];
reg [3:0] S;
wire [31:0] Y;
integer i;
reg [31:0] result [0:15];
MUX32_16x1 mux_inst_01(.Y(Y),
.I0(I[0]), .I1(I[1]), .I2(I[2]), .I3(I[3]),
.I4(I[4]), .I5(I[5]), .I6(I[6]), .I7(I[7]),
.I8(I[8]), .I9(I[9]), .I10(I[10]), .I11(I[11]),
.I12(I[12]), .I13(I[13]), .I14(I[14]), .I15(I[15]),
.S(S));
initial
begin
for(i=0;i<16;i=i+1)
I[i]=i;
for(i=0;i<16;i=i+1)
begin
#1 S = i;
#1 result[i]=Y;
end
#1
$writememh("./OUTPUT/mux32_16x1_tb.out", result);
$stop;
end
endmodule
module MUX32_2x1_TB;
reg [31:0] I0, I1;
reg S;
wire [31:0] Y;
reg [31:0] result [0:1];
MUX32_2x1 mux_inst_01(.Y(Y), .I0(I0), .I1(I1), .S(S));
initial
begin
I0 = 32'hA5A5A5A5; I1 = 32'h5A5A5A5A; S=1'b0;
#1 result[0] = Y;
#1 S=1'b1;
#1 result[1] = Y;
#1
$writememh("./OUTPUT/mux32_2x1_tb.out", result);
$stop;
end
endmodule

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// Name: rc_add_sub_32_tb.v
// Module: RC_ADD_SUB_32_TB
//
// Notes: - Testbench for RC adder/asubtractor
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module RC_ADD_SUB_32_TB;
// driver
reg [`DATA_INDEX_LIMIT:0] A;
reg [`DATA_INDEX_LIMIT:0] B;
reg SnA;
// outputs to observe
wire CO;
wire [`DATA_INDEX_LIMIT:0] Y;
integer i;
reg [`DATA_INDEX_LIMIT:0] result[0:4];
RC_ADD_SUB_32 rc_add_sub_inst(.Y(Y), .CO(CO), .A(A), .B(B), .SnA(SnA));
initial
begin
i=0;
A=10; B=20; SnA=1'b0; // Y = 10 + 20 = 30
#1 result[i] = Y; i=i+1;
#1 A=10; B=20; SnA=1'b1; // Y = 10 - 20 = -10
#1 result[i] = Y; i=i+1;
#1 A=15; B=12; SnA=1'b1; // Y = 15 - 12 = 3
#1 result[i] = Y; i=i+1;
#1 A=0; B=4; SnA=1'b0; // Y = 0 + 4 = 4
#1 result[i] = Y; i=i+1;
#1 A=32'h80001234; B=32'h80004321; SnA=1'b0;
#1 result[i] = Y; i=i+1;
#1
$writememh("./OUTPUT/rc_add_sub_32.out",result);
$stop;
end
endmodule

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// Name: proj_2_tb.v
// Module: RF_TB
//
//
// Monitors: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
// READ : Read signal
// WRITE: Write signal
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - Testbench for MEMORY_64MB memory system
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
`include "../prj_definition.v"
module RF_TB;
// Storage list
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_W;
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1;
reg [`REG_ADDR_INDEX_LIMIT:0] ADDR_R2;
// reset
reg READ, WRITE, RST;
// data register
reg [`DATA_INDEX_LIMIT:0] DATA_REG;
integer i; // index for memory operation
integer no_of_test, no_of_pass;
integer load_data;
// wire lists
wire CLK;
wire [`DATA_INDEX_LIMIT:0] DATA_R1;
wire [`DATA_INDEX_LIMIT:0] DATA_R2;
// result
integer ridx;
reg [`DATA_INDEX_LIMIT:0] result [0:63];
// Clock generator instance
CLK_GENERATOR clk_gen_inst(.CLK(CLK));
// 64MB memory instance
REGISTER_FILE_32x32 ref_32x32_inst(.DATA_R1(DATA_R1), .DATA_R2(DATA_R2), .ADDR_R1(ADDR_R1),
.ADDR_R2(ADDR_R2), .DATA_W(DATA_REG), .ADDR_W(ADDR_W),
.READ(READ), .WRITE(WRITE), .CLK(CLK), .RST(RST));
initial
begin
ridx=0;
RST=1'b1;
READ=1'b0;
WRITE=1'b0;
DATA_REG = {`DATA_WIDTH{1'b0} };
ADDR_R1 = {`DATA_WIDTH{1'b0} };
ADDR_R2 = {`DATA_WIDTH{1'b0} };
no_of_test = 0;
no_of_pass = 0;
// Start the operation
#10 RST=1'b0;
#10 RST=1'b1;
// Write cycle
for(i=0;i<32; i = i + 1)
begin
#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
end
#5 READ=1'b0; WRITE=1'b0;
// test of write data
for(i=0;i<32; i = i + 1)
begin
#5 READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
#5 no_of_test = no_of_test + 1;
if (DATA_R1 !== i)
$write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
else
no_of_pass = no_of_pass + 1;
result[ridx] = DATA_R1; ridx=ridx+1;
result[ridx] = DATA_R1; ridx=ridx+1;
end
#5 READ=1'b0; WRITE=1'b0; // No op
#10 $write("\n");
$write("\tTotal number of tests %d\n", no_of_test);
$write("\tTotal number of pass %d\n", no_of_pass);
$write("\n");
$writememh("./OUTPUT/rf_tb.out",result);
$stop;
end
endmodule