diff --git a/register_file.v b/register_file.v
index cb430ba..76796b3 100644
--- a/register_file.v
+++ b/register_file.v
@@ -41,6 +41,31 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// TBD
+// module REG32(Q, D, LOAD, CLK, RESET);
+// module DECODER_5x32(D,I);
+
+// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
+                     // I8, I9, I10, I11, I12, I13, I14, I15,
+                     // I16, I17, I18, I19, I20, I21, I22, I23,
+                     // I24, I25, I26, I27, I28, I29, I30, I31, S);
+
+wire [31:0] Q [31:0];
+wire [31:0] write;
+DECODER_5x32 d_write(write, ADDR_W);
+
+REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
+
+MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R1
+);
+MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
+                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
+                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
+                     ADDR_R2
+);
 
 endmodule