lab-04: signed mult working

Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32

TESTBENCH/mult_tb.v

@@ -36,6 +36,8 @@ A=10; B=20;     // Y = 10 * 20 = 200
 #1 result[i] = {HI,LO}; i=i+1;
 #1 A=10; B=19; 	// Y = 10 * 19 = 190
 #1 result[i] = {HI,LO}; i=i+1;
+#1 A=32'h00d96027; B=32'h7c32b43c; 	// Y = 0x0d96027 * 0x7c32b43c = 0x 006975a0 b62bf524
+#1 result[i] = {HI,LO}; i=i+1;
 #1 A=32'h70000000; B=32'h70000000; 
 #1 result[i] = {HI,LO}; i=i+1;
 #1 

full_adder.v

@@ -23,6 +23,9 @@ module FULL_ADDER(S,CO,A,B, CI);
 output S,CO;
 input A,B, CI;
 
-//TBD
+wire Y, CO1, CO2;
+HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
+HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
+or (CO, CO1, CO2);
 
-endmodule;
+endmodule

half_adder.v

@@ -22,6 +22,7 @@ module HALF_ADDER(Y,C,A,B);
 output Y,C;
 input A,B;
 
-// TBD
+xor digit(Y, A, B);
+and carry(C, A, B);
 
-endmodule;
+endmodule

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-// TBD
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -31,7 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-// TBD
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
 
 endmodule
 

logic_32_bit.v

@@ -80,3 +80,19 @@ generate
     end
 endgenerate
 endmodule
+
+// 32-bit buffer
+module BUF32_1x1(Y,A);
+//output 
+output [31:0] Y;
+//input
+input [31:0] A;
+
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1)
+    begin : buf32_gen_loop
+        buf buf32_inst(Y[i], A[i]);
+    end
+endgenerate
+endmodule

mult.v

@@ -27,7 +27,25 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;
 
-// TBD
+wire [31:0] A_neg, B_neg;
+TWOSCOMP32 A_twoscomp(A_neg, A);
+TWOSCOMP32 B_twoscomp(B_neg, B);
+
+wire [31:0] A_abs, B_abs;
+MUX32_2x1 A_mux(A_abs, A, A_neg, A[31]);
+MUX32_2x1 B_mux(B_abs, B, B_neg, B[31]);
+
+wire [31:0] HI_abs, LO_abs;
+MULT32_U mult_abs(HI_abs, LO_abs, A_abs, B_abs);
+
+wire [31:0] HI_neg, LO_neg;
+TWOSCOMP64 mult_neg({HI_neg,LO_neg}, {HI_abs,LO_abs});
+
+wire sign;
+xor (sign, A[31], B[31]);
+
+MUX32_2x1 HI_mux(HI, HI_abs, HI_neg, sign);
+MUX32_2x1 LO_mux(LO, LO_abs, LO_neg, sign);
 
 endmodule
 
@@ -39,6 +57,37 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;
 
-// TBD
+// partial sums
+wire [31:0] Y [31:0];
+
+// first partial is just
+AND32_2x1 partial_1(Y[0], A, {32{B[0]}});
+// put lowest bit from first partial into result
+buf (LO[0], Y[0][0]);
+
+
+// carries from partial adders
+wire CI[31:0];
+// first carry is always 0
+buf (CI[0], 0);
+
+genvar i;
+generate
+    for (i = 0; i < 31; i = i + 1)
+    begin : mult32u_gen_loop
+        // multiply A by a single digit in B
+        wire [31:0] A_and;
+        AND32_2x1 partial_and_inst(A_and, A, {32{B[i+1]}});
+
+        // calc the next partial and carry (i + 1)
+        RC_ADD_SUB_32 partial_add_inst(.Y(Y[i+1]), .CO(CI[i+1]), .A(A_and), .B({CI[i],Y[i][31:1]}), .SnA(1'b0));
+
+        // put lowest bit from calc into result
+        buf (LO[i+1], Y[i+1][0]);
+    end
+endgenerate
+
+// last carry and partial is HI
+BUF32_1x1 buf_hi(HI, {CI[31],Y[31][31:1]});
 
 endmodule

mux.v

@@ -102,7 +102,20 @@ input [31:0] I0;
 input [31:0] I1;
 input S;
 
-// TBD
+// only need 1 not gate
+not (S_not, S);
+
+wire [31:0] x0, x1;
+
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1)
+    begin : mux32_gen_loop
+        and (x0[i], S_not, I0[i]);
+        and (x1[i], S, I1[i]);
+        or (Y[i], x0[i], x1[i]);
+    end
+endgenerate
 
 endmodule
 
@@ -113,6 +126,9 @@ output Y;
 //input list
 input I0, I1, S;
 
-// TBD
+not (S_not, S);
+and (x0, S_not, I0);
+and (x1, S, I1);
+or (Y, x0, x1);
 
 endmodule

rc_add_sub_32.v

@@ -29,7 +29,21 @@ input [63:0] A;
 input [63:0] B;
 input SnA;
 
-// TBD
+// carry-in bits for each 1-bit full adder
+wire C[0:64];
+buf (C[0], SnA);
+
+genvar i;
+generate
+    for (i = 0; i < 64; i = i + 1)
+    begin : add64_gen_loop
+        wire B_xor;
+        xor (B_xor, B[i], SnA);
+        FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
+    end
+endgenerate
+
+buf (CO, C[64]);
 
 endmodule
 
@@ -42,7 +56,20 @@ input [`DATA_INDEX_LIMIT:0] A;
 input [`DATA_INDEX_LIMIT:0] B;
 input SnA;
 
-// TBD
+// carry-in bits for each 1-bit full adder
+wire C[0:32];
+buf (C[0], SnA);
+
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1)
+    begin : add32_gen_loop
+        wire B_xor;
+        xor (B_xor, B[i], SnA);
+        FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
+    end
+endgenerate
+
+buf (CO, C[32]);
 
 endmodule
-