implement a Verilog gate level model for ripple carry adder subtractor

Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 
@@ -31,7 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 

rc_add_sub_32.v

@@ -29,21 +29,7 @@ input [63:0] A;
 input [63:0] B;
 input SnA;
 
-// carry-in bits for each 1-bit full adder
+// TBD
-wire C[0:64];
-buf (C[0], SnA);
-
-genvar i;
-generate
-    for (i = 0; i < 64; i = i + 1)
-    begin : add64_gen_loop
-        wire B_xor;
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
-    end
-endgenerate
-
-buf (CO, C[64]);
 
 endmodule
 
@@ -64,12 +50,11 @@ genvar i;
 generate
     for (i = 0; i < 32; i = i + 1)
     begin : add32_gen_loop
-        wire B_xor;
+        FULL_ADDER add_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
     end
 endgenerate
 
+//assign CO = C[32];
 buf (CO, C[32]);
 
 endmodule