2 Commits

Author	SHA1	Message	Date
Iurii Tatishchev	87e48f162e	implement a Verilog gate level model for 32-bit basic logic gates ... Gate level implementation for the following components: - NOR32_2x1 - AND32_2x1 - INV32_1x1 - OR32_2x1	2024-10-01 10:44:45 -07:00
Iurii Tatishchev	5520d6d716	initial commit	2024-10-01 10:39:56 -07:00