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control unit: more progress, fibonacci working

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This commit is contained in:
Yuri Tatishchev 2024-11-18 00:47:16 -08:00
parent 2ffd8c9424
commit b651f04748
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
6 changed files with 42 additions and 35 deletions
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12
OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat
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@ -1,9 +1,9 @@
// memory data file (do not edit the following line - required for mem load use) // memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000 00000001
00000000 00000004
00000000 00000004
00000000 00000010
00000000 00000010
00000000 00000040

2
OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat
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@ -6,4 +6,4 @@
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000200

22
OUTPUT/CS147_SP17_HW01_02_mem_dump.dat
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@ -1,14 +1,14 @@
// memory data file (do not edit the following line - required for mem load use) // memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000000a 00090001
0000000b 00090003
0000000c 00090005
0000000d 00090007
0000000e 00090009
0000000f 0009000b
00000010 0009000d
00000011 0009000f
00000012 00090011
00000013 00090013
00000000 00090015

2
OUTPUT/RevFib_mem_dump.dat
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@ -16,4 +16,4 @@
00000000 00000000
00000000 00000000
00000000 00000000
00000000 00000059

30
OUTPUT/fibonacci_mem_dump.dat
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@ -2,18 +2,18 @@
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m // instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress // format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000 00000000
00000000 00000001
00000000 00000001
00000000 00000002
00000000 00000003
00000000 00000005
00000000 00000008
00000000 0000000d
00000000 00000015
00000000 00000022
00000000 00000037
00000000 00000059
00000000 00000090
00000000 000000e9
00000000 00000179
00000000 00000262

9
control_unit.v
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@ -171,6 +171,8 @@ endtask
reg read, write; reg read, write;
buf (READ, read); buf (READ, read);
buf (WRITE, write); buf (WRITE, write);
//assign READ = read;
//assign WRITE = write;
reg [31:0] C; reg [31:0] C;
@ -313,13 +315,18 @@ always @ (state) begin
// wd_sel_3 - pc_inc or wd_sel_2 // wd_sel_3 - pc_inc or wd_sel_2
// jal - pc_inc, else wd_sel_2 // jal - pc_inc, else wd_sel_2
C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1; C[`wd_sel_3] = opcode == 6'h03 ? 1'b0 : 1'b1;
// ma_sel_1 - alu_out for lw or sw, sp for push or pop
C[`ma_sel_1] = opcode == `OP_LW || opcode == `OP_SW ? 1'b0 : 1'b1;
// ma_sel_2 - 1 for pc, 0 for everything else
C[`ma_sel_2] = opcode == `OP_LW || opcode == `OP_SW || opcode == `OP_PUSH || opcode == `OP_POP ? 1'b0 : 1'b1;
// md_sel_1 - r1 for push, r2 for sw // md_sel_1 - r1 for push, r2 for sw
C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0; C[`md_sel_1] = opcode == 6'h1b ? 1'b1 : 1'b0;
end end
`PROC_MEM: begin `PROC_MEM: begin
// load now // load now
// push or sw - write to memory // push or sw - write to memory
if (opcode == 6'h1b || opcode == 6'h2b) begin if (opcode == `OP_PUSH || opcode == `OP_SW) begin
read = 1'b0; read = 1'b0;
write = 1'b1; write = 1'b1;
end end