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(WIP): REG1

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Yuri Tatishchev
2024-10-19 15:54:51 -07:00
parent 7c0645eaa1
commit a110f7c042
1 changed files with 4 additions and 1 deletions
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logic.v
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@@ -56,7 +56,10 @@ input D, C, L;
input nP, nR; input nP, nR;
output Q,Qbar; output Q,Qbar;
// TBD wire D_out;
MUX1_2x1 data(D_out, Q, D, L);
D_FF dff(Q, Qbar, D_out, C, nP, nR);
endmodule endmodule