From 7e4a63e1556274e7227e88bcb27570777062bbda Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Sat, 19 Oct 2024 16:51:30 -0700 Subject: [PATCH] (WIP) lab-08: Decoder_5x32, Mux32_32x1 --- logic.v | 41 ++++++++++++++++++++++++++++++++++++++--- mux.v | 11 ++++++++++- 2 files changed, 48 insertions(+), 4 deletions(-) diff --git a/logic.v b/logic.v index 4db1f09..105363a 100644 --- a/logic.v +++ b/logic.v @@ -127,7 +127,19 @@ output [31:0] D; // input input [4:0] I; -// TBD +wire [15:0] half; +wire I_not; +not I_inv(I_not, I[4]); + +DECODER_4x16 d(half, I[3:0]); + +genvar i; +generate + for (i = 0; i < 16; i = i + 1) begin : d5_gen + and msb0(D[i], I_not, half[i]); + and msb1(D[i + 16], I[4], half[i]); + end +endgenerate endmodule @@ -138,7 +150,19 @@ output [15:0] D; // input input [3:0] I; -// TBD +wire [7:0] half; +wire I_not; +not I_inv(I_not, I[3]); + +DECODER_3x8 d(half, I[2:0]); + +genvar i; +generate + for (i = 0; i < 8; i = i + 1) begin : d4_gen + and msb0(D[i], I_not, half[i]); + and msb1(D[i + 8], I[3], half[i]); + end +endgenerate endmodule @@ -150,8 +174,19 @@ output [7:0] D; // input input [2:0] I; -//TBD +wire [3:0] half; +wire I_not; +not I_inv(I_not, I[2]); +DECODER_2x4 d(half, I[1:0]); + +genvar i; +generate + for (i = 0; i < 4; i = i + 1) begin : d3_gen + and msb0(D[i], I_not, half[i]); + and msb1(D[i + 4], I[2], half[i]); + end +endgenerate endmodule diff --git a/mux.v b/mux.v index 32e7d11..6e2ffeb 100644 --- a/mux.v +++ b/mux.v @@ -27,7 +27,16 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23; input [31:0] I24, I25, I26, I27, I28, I29, I30, I31; input [4:0] S; -// TBD +wire [31:0] x0, x1; +MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7, + I8, I9, I10, I11, I12, I13, I14, I15, + S[3:0] +); +MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23, + I24, I25, I26, I27, I28, I29, I30, I31, + S[3:0] +); +MUX32_2x1 out(Y, x0, x1, S[4]); endmodule