From 3801d523de44d6b5ef13af121f87000f0666320e Mon Sep 17 00:00:00 2001
From: Iurii Tatishchev <itatishch@gmail.com>
Date: Tue, 1 Oct 2024 20:42:02 -0700
Subject: [PATCH] implement a Verilog gate level model for ripple carry adder
 subtractor

Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32
---
 full_adder.v    | 12 +-----------
 half_adder.v    |  9 ++-------
 rc_add_sub_32.v | 13 ++++---------
 3 files changed, 7 insertions(+), 27 deletions(-)

diff --git a/full_adder.v b/full_adder.v
index f1d516f..1e4d4f0 100644
--- a/full_adder.v
+++ b/full_adder.v
@@ -23,19 +23,9 @@ module FULL_ADDER(S,CO,A,B, CI);
 output S,CO;
 input A,B, CI;
 
-// half adder 1
-//assign Y = A ^ B;
-//assign CO1 = A & B;
-
-// half adder 2
-//assign S = Y ^ CI;
-//assign CO2 = Y & CI;
-
-//assign CO = CO1 | CO2;
-
 wire Y, CO1, CO2;
 HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
 HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
-assign CO = CO1 | CO2;
+or (CO, CO1, CO2);
 
 endmodule
diff --git a/half_adder.v b/half_adder.v
index f9ab344..64e4afb 100644
--- a/half_adder.v
+++ b/half_adder.v
@@ -22,12 +22,7 @@ module HALF_ADDER(Y,C,A,B);
 output Y,C;
 input A,B;
 
-// this
-assign Y = A ^ B;
-assign C = A & B;
-
-// or this
-//xor digit(Y, A, B);
-//and carry(C, A, B);
+xor digit(Y, A, B);
+and carry(C, A, B);
 
 endmodule
diff --git a/rc_add_sub_32.v b/rc_add_sub_32.v
index 0fd1e62..03840b4 100644
--- a/rc_add_sub_32.v
+++ b/rc_add_sub_32.v
@@ -42,15 +42,9 @@ input [`DATA_INDEX_LIMIT:0] A;
 input [`DATA_INDEX_LIMIT:0] B;
 input SnA;
 
-//wire C0, C1, C2, C3;
-//assign C0 = SnA;
-//FULL_ADDER b0(Y[0], C1, A[0], B[0], C0);
-
-// module FULL_ADDER(S,CO,A,B, CI);
-
-// carry-in bits for each 1 bit full adder
+// carry-in bits for each 1-bit full adder
 wire C[0:32];
-assign C[0] = SnA;
+buf (C[0], SnA);
 
 genvar i;
 generate
@@ -60,6 +54,7 @@ generate
     end
 endgenerate
 
-assign CO = C[32];
+//assign CO = C[32];
+buf (CO, C[32]);
 
 endmodule