Yuri Tatishchev
5a4b5a312a
Gate level implementation for the following components: - MULT32_U - MULT32 - MUX32_2x1
94 lines
2.1 KiB
Verilog
94 lines
2.1 KiB
Verilog
// Name: mult.v
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// Module: MULT32 , MULT32_U
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//
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// Output: HI: 32 higher bits
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// LO: 32 lower bits
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//
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//
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// Input: A : 32-bit input
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// B : 32-bit input
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//
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// Notes: 32-bit multiplication
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module MULT32(HI, LO, A, B);
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// output list
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output [31:0] HI;
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output [31:0] LO;
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// input list
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input [31:0] A;
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input [31:0] B;
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wire [31:0] A_neg, B_neg;
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TWOSCOMP32 A_twoscomp(A_neg, A);
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TWOSCOMP32 B_twoscomp(B_neg, B);
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wire [31:0] A_abs, B_abs;
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MUX32_2x1 A_mux(A_abs, A, A_neg, A[31]);
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MUX32_2x1 B_mux(B_abs, B, B_neg, B[31]);
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wire [31:0] HI_abs, LO_abs;
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MULT32_U mult_abs(HI_abs, LO_abs, A_abs, B_abs);
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wire [31:0] HI_neg, LO_neg;
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TWOSCOMP64 mult_neg({HI_neg,LO_neg}, {HI_abs,LO_abs});
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wire sign;
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xor (sign, A[31], B[31]);
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MUX32_2x1 HI_mux(HI, HI_abs, HI_neg, sign);
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MUX32_2x1 LO_mux(LO, LO_abs, LO_neg, sign);
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endmodule
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module MULT32_U(HI, LO, A, B);
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// output list
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output [31:0] HI;
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output [31:0] LO;
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// input list
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input [31:0] A;
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input [31:0] B;
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// partial sums
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wire [31:0] Y [31:0];
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// first partial is just
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AND32_2x1 partial_1(Y[0], A, {32{B[0]}});
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// put lowest bit from first partial into result
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buf (LO[0], Y[0][0]);
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// carries from partial adders
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wire CI[31:0];
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// first carry is always 0
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buf (CI[0], 0);
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genvar i;
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generate
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for (i = 0; i < 31; i = i + 1)
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begin : mult32u_gen_loop
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// multiply A by a single digit in B
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wire [31:0] A_and;
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AND32_2x1 partial_and_inst(A_and, A, {32{B[i+1]}});
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// calc the next partial and carry (i + 1)
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RC_ADD_SUB_32 partial_add_inst(.Y(Y[i+1]), .CO(CI[i+1]), .A(A_and), .B({CI[i],Y[i][31:1]}), .SnA(1'b0));
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// put lowest bit from calc into result
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buf (LO[i+1], Y[i+1][0]);
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end
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endgenerate
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// last carry and partial is HI
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BUF32_1x1 buf_hi(HI, {CI[31],Y[31][31:1]});
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endmodule
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