33 lines
775 B
Verilog
33 lines
775 B
Verilog
// Name: clk_gen.v
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// Module: CLK_GENERATOR
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//
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// Output: CLK - output clock with period `SYS_CLK_FREQ
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//
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// Notes: Clock generator. The clock frequency is defined in the project definition file.
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module CLK_GENERATOR(CLK);
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// output list;
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output CLK;
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// storage for clock value
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reg CLK;
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initial
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begin
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CLK = 1'b1;
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end
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// For ever perform the following task.
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always
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begin
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#`SYS_CLK_HALF_PERIOD CLK <= ~CLK;
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end
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endmodule;
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