Yuri Tatishchev
1ab4ea027d
Gate level implementation for the following components: - SHIFT32_L - SHIFT32_R - BARREL_SHIFTER32 - SHIFT32
113 lines
2.5 KiB
Verilog
113 lines
2.5 KiB
Verilog
// Name: barrel_shifter.v
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// Module: SHIFT32_L , SHIFT32_R, SHIFT32
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//
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// Notes: 32-bit barrel shifter
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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// 32-bit shift amount shifter
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module SHIFT32(Y,D,S, LnR);
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// output list
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output [31:0] Y;
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// input list
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input [31:0] D;
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input [31:0] S;
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input LnR;
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// check if upper bits are nonzero
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wire oob [31:5];
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buf (oob[5], S[5]);
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genvar i;
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generate
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for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
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or (oob[i], oob[i-1], S[i]);
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end
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endgenerate
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wire [31:0] shifted;
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BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
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// return 0 if S >= 32
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MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
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endmodule
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// Shift with control L or R shift
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module BARREL_SHIFTER32(Y,D,S, LnR);
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// output list
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output [31:0] Y;
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// input list
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input [31:0] D;
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input [4:0] S;
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input LnR;
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wire [31:0] shifters [1:0];
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SHIFT32_R shifter_r(shifters[0], D, S);
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SHIFT32_L shifter_l(shifters[1], D, S);
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MUX32_2x1 mux_lnr(Y, shifters[0], shifters[1], LnR);
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endmodule
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// Right shifter
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module SHIFT32_R(Y,D,S);
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// output list
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output [31:0] Y;
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// input list
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input [31:0] D;
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input [4:0] S;
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wire [31:0] stages [5:0];
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buf stage0[31:0] (stages[0], D);
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genvar i, j;
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generate
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for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
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for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
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if (j < 32 - (2 ** i))
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MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j + (2 ** i)], S[i]);
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else
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MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
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end
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end
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endgenerate
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buf out[31:0] (Y, stages[5]);
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endmodule
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// Left shifter
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module SHIFT32_L(Y,D,S);
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// output list
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output [31:0] Y;
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// input list
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input [31:0] D;
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input [4:0] S;
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wire [31:0] stages [5:0];
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buf stage0[31:0] (stages[0], D);
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genvar i, j;
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generate
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for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
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for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
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if (j >= (2 ** i))
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MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j - (2 ** i)], S[i]);
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else
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MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
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end
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end
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endgenerate
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buf out[31:0] (Y, stages[5]);
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endmodule
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