343 lines
6.9 KiB
Verilog
343 lines
6.9 KiB
Verilog
// Name: logic_tb.v
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// Module: TWOSCOMP32_TB,
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// TWOSCOMP64_TB,
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// SR_LATCH_TB,
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// D_LATCH_TB,
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// D_FF_PE_TB,
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// REG1_TB,
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// REG32_TB,
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// DECODER_5x32_TB
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//
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// Notes: - Testbench for multiplier
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module DECODER_5x32_TB;
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// observer
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wire [31:0] D;
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// driver
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reg [4:0] I;
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// result
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integer i, idx;
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reg [31:0] result[0:31];
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DECODER_5x32 decoder_5x32_inst0(.D(D),.I(I));
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initial
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begin
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i=0;
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for(idx=0; idx<32; idx = idx + 1)
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begin
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#1 I=idx;
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#1 result[i] = D; i=i+1;
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end
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#1
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$writememb("./OUTPUT/decoder_5x32_tb.out",result);
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$stop;
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end
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endmodule
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module REG32_TB;
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//driver
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reg [`DATA_INDEX_LIMIT:0] D;
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reg LOAD, RESET;
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// oberver
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wire [`DATA_INDEX_LIMIT:0] Q;
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// clock
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wire clk;
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// Result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:7];
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CLK_GENERATOR clk_gen_inst(.CLK(clk));
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REG32 reg32_inst(.Q(Q), .CLK(clk), .LOAD(LOAD), .D(D), .RESET(RESET));
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initial
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begin
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i=0; RESET=1; D=32'ha5a5a5a5; LOAD=0;
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// Reset
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#1 D=32'ha5a5a5a5; LOAD=0; RESET=0;
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#1 result[i] = Q; i=i+1;
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// Hold
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#1 D=32'ha5a5a5a5; LOAD=0; RESET=1;
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#1 result[i] = Q; i=i+1;
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// Normal operation
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#6 D=32'ha5a5a5a5; LOAD=1; RESET=1;
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#5 result[i] = Q; i=i+1;
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#5 D=32'hffff0000; LOAD=1; RESET=1;
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#5 result[i] = Q; i=i+1;
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// Reset
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#1 D=32'h0000ffff; LOAD=1; RESET=0;
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#1 result[i] = Q; i=i+1;
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// Normal operation
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#9 D=32'h0000ffff; LOAD=1; RESET=1;
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#1 result[i] = Q; i=i+1;
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#10 result[i] = Q; i=i+1;
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#10 D=32'h5a5a5a5a; LOAD=0; RESET=1;
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#10
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result[i] = Q; i=i+1;
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$writememh("./OUTPUT/d_reg32_tb.out",result);
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$stop;
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end
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endmodule
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module REG1_TB;
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//driver
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reg D, L, nP, nR;
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// oberver
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wire Q,Qbar;
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// clock
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wire clk;
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// Result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:6];
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CLK_GENERATOR clk_gen_inst(.CLK(clk));
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REG1 reg1_inst(.Q(Q), .Qbar(Qbar), .C(clk),
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.L(L), .D(D), .nP(nP), .nR(nR));
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initial
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begin
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i=0; nP=1; nR=1; D=0; L=0;
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// Preset
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#1 D=0; L=0; nP=0; nR=1;
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#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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// Hold
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#1 D=0; L=0; nP=1; nR=1;
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#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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// Normal operation
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#6 D=0; L=1; nP=1; nR=1;
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#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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#5 D=1; L=1; nP=1; nR=1;
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#5 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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// Reset
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#1 D=1; L=1; nP=1; nR=0;
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#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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// Normal operation
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#9 D=1; L=1; nP=1; nR=1;
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#1 result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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#10 D=0; L=0; nP=1; nR=1;
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#10
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result[i] = {Q,Qbar,D,L,nR,nP}; i=i+1;
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$writememh("./OUTPUT/d_reg1_tb.out",result);
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$stop;
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end
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endmodule
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module D_FF_TB;
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//driver
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reg D, nP, nR;
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// oberver
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wire Q,Qbar;
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// clock
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wire clk;
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// Result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:6];
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CLK_GENERATOR clk_gen_inst(.CLK(clk));
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D_FF d_ff_inst(.Q(Q), .Qbar(Qbar), .C(clk),
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.D(D), .nP(nP), .nR(nR));
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initial
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begin
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i=0; nP=1; nR=1; D=0;
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// Preset
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#1 D=0; nP=0; nR=1;
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#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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// Hold
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#1 D=0; nP=1; nR=1;
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#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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// Normal operation
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#6 D=0; nP=1; nR=1;
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#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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#5 D=1; nP=1; nR=1;
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#5 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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// Reset
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#1 D=1; nP=1; nR=0;
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#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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// Normal operation
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#9 D=1; nP=1; nR=1;
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#1 result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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#10
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result[i] = {Q,Qbar,D,nR,nP}; i=i+1;
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$writememh("./OUTPUT/d_ff_tb.out",result);
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$stop;
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end
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endmodule
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module D_LATCH_TB;
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// driver
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reg D, C, nP, nR;
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// oberver
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wire Q,Qbar;
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// Result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:7];
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D_LATCH d_latch_inst(.Q(Q), .Qbar(Qbar), .D(D),
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.C(C), .nP(nP), .nR(nR));
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initial
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begin
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i=0;
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// Normal preset
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#1 C=0; D=0; nR=1; nP=0; // Q=1
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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// Hold 1 on C=0
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#1 C=0; D=0; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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#1 C=0; D=1; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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// Normal reset
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#1 C=0; D=0; nR=0; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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// Hold 0 on C=0
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#1 C=0; D=0; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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#1 C=0; D=1; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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// Set on clock
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#1 C=1; D=1; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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// Reset on clock
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#1 C=1; D=0; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,D,nR,nP}; i=i+1;
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#1
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$writememh("./OUTPUT/d_latch_tb.out",result);
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$stop;
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end
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endmodule
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module SR_LATCH_TB;
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// driver
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reg S, R, C, nP, nR;
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// oberver
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wire Q,Qbar;
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// Result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:13];
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SR_LATCH sr_latch_inst(.Q(Q), .Qbar(Qbar), .S(S),
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.R(R), .C(C), .nP(nP), .nR(nR));
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initial
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begin
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i=0;
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// Normal reset preset
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#1 C=0; S=0; R=0; nR=1; nP=0; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Hold 1 on C=0
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#1 C=0; S=0; R=0; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=0; R=1; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=1; R=0; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=1; R=1; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Normal reset
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#1 C=0; S=0; R=0; nR=0; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Hold 0 on C=0
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#1 C=0; S=0; R=0; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=0; R=1; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=1; R=0; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1 C=0; S=1; R=1; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Set on clock
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#1 C=1; S=1; R=0; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Hold
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#1 C=1; S=0; R=0; nR=1; nP=1; // Q=1
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Reset on clock
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#1 C=1; S=0; R=1; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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// Hold
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#1 C=1; S=0; R=0; nR=1; nP=1; // Q=0
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#1 result[i] = {Q,Qbar,C,S,R,nR,nP}; i=i+1;
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#1
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$writememh("./OUTPUT/sr_latch_tb.out",result);
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$stop;
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end
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endmodule
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module TWOSCOMP32_TB;
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// driver
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reg [`DATA_INDEX_LIMIT:0] A;
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// wire
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wire [`DATA_INDEX_LIMIT:0] Y;
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// result
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:1];
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TWOSCOMP32 inst_2scomp_01(.Y(Y), .A(A));
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initial
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begin
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i=0;
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A = 10;
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#1 result[i] = Y; i = i + 1;
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#1 A=-5;
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#1 result[i] = Y; i = i + 1;
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#1
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$writememh("./OUTPUT/twoscomp32_tb.out",result);
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$stop;
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end
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endmodule
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module TWOSCOMP64_TB;
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// driver
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reg [`DOUBLE_DATA_INDEX_LIMIT:0] A;
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// wire
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wire [`DOUBLE_DATA_INDEX_LIMIT:0] Y;
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// result
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integer i;
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reg [`DOUBLE_DATA_INDEX_LIMIT:0] result[0:1];
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TWOSCOMP64 inst_2scomp_01(.Y(Y), .A(A));
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initial
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begin
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i=0;
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A = 10;
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#1 result[i] = Y; i = i + 1;
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#1 A=-5;
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#1 result[i] = Y; i = i + 1;
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#1
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$writememh("./OUTPUT/twoscomp64_tb.out",result);
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$stop;
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end
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endmodule |