45 lines
858 B
Verilog
45 lines
858 B
Verilog
// Name: mult.v
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// Module: MULT32 , MULT32_U
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//
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// Output: HI: 32 higher bits
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// LO: 32 lower bits
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//
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//
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// Input: A : 32-bit input
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// B : 32-bit input
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//
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// Notes: 32-bit multiplication
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module MULT32(HI, LO, A, B);
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// output list
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output [31:0] HI;
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output [31:0] LO;
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// input list
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input [31:0] A;
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input [31:0] B;
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// TBD
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endmodule
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module MULT32_U(HI, LO, A, B);
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// output list
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output [31:0] HI;
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output [31:0] LO;
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// input list
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input [31:0] A;
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input [31:0] B;
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// TBD
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endmodule
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