35 lines
1.0 KiB
Verilog
35 lines
1.0 KiB
Verilog
// Name: data_path.v
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// Module: DATA_PATH
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// Output: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - 32 bit processor implementing cs147sec05 instruction set
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST);
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// output list
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output [`ADDRESS_INDEX_LIMIT:0] ADDR;
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output ZERO;
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output [`DATA_INDEX_LIMIT:0] DATA_OUT, INSTRUCTION;
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// input list
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input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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input CLK, RST;
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input [`DATA_INDEX_LIMIT:0] DATA_IN;
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// TBD
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endmodule
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