cs147dv/data_path.v
2024-10-01 10:39:56 -07:00

35 lines
1.0 KiB
Verilog

// Name: data_path.v
// Module: DATA_PATH
// Output: DATA : Data to be written at address ADDR
// ADDR : Address of the memory location to be accessed
//
// Input: DATA : Data read out in the read operation
// CLK : Clock signal
// RST : Reset signal
//
// Notes: - 32 bit processor implementing cs147sec05 instruction set
//
// Revision History:
//
// Version Date Who email note
//------------------------------------------------------------------------------------------
// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
//------------------------------------------------------------------------------------------
//
`include "prj_definition.v"
module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST);
// output list
output [`ADDRESS_INDEX_LIMIT:0] ADDR;
output ZERO;
output [`DATA_INDEX_LIMIT:0] DATA_OUT, INSTRUCTION;
// input list
input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
input CLK, RST;
input [`DATA_INDEX_LIMIT:0] DATA_IN;
// TBD
endmodule