47 lines
1.6 KiB
Verilog
47 lines
1.6 KiB
Verilog
// Name: processor.v
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// Module: PROC_CS147_SEC05
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// Output: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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// READ : Read signal
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// WRITE: Write signal
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - 32 bit processor implementing cs147sec05 instruction set
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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// 1.1 Oct 19, 2014 Kaushik Patra kpatra@sjsu.edu Fixed the RF connection
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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module PROC_CS147_SEC05(DATA_OUT, ADDR, DATA_IN, READ, WRITE, CLK, RST);
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// output list
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output [`ADDRESS_INDEX_LIMIT:0] ADDR;
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output [`DATA_INDEX_LIMIT:0] DATA_OUT;
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output READ, WRITE;
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// input list
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input CLK, RST;
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input [`DATA_INDEX_LIMIT:0] DATA_IN;
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// net section
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wire zero;
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wire [`CTRL_WIDTH_INDEX_LIMIT:0] ctrl;
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wire [`DATA_INDEX_LIMIT:0] INSTRUCTION;
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// instantiation section
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// Control unit
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CONTROL_UNIT cu_inst (.CTRL(ctrl), .READ(READ), .WRITE(WRITE),
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.ZERO(zero), .INSTRUCTION(INSTRUCTION),
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.CLK(CLK), .RST(RST));
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// data path
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DATA_PATH data_path_inst (.DATA_OUT(DATA_OUT), .INSTRUCTION(INSTRUCTION), .DATA_IN(DATA_IN), .ADDR(ADDR), .ZERO(zero),
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.CTRL(ctrl), .CLK(CLK), .RST(RST));
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endmodule; |