Yuri Tatishchev
5a4b5a312a
Gate level implementation for the following components: - MULT32_U - MULT32 - MUX32_2x1
99 lines
1.6 KiB
Verilog
Executable File
99 lines
1.6 KiB
Verilog
Executable File
// Name: logic_32_bit.v
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// Module:
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// Input:
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// Output:
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//
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// Notes: Common definitions
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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// 32-bit NOR
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module NOR32_2x1(Y,A,B);
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//output
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output [31:0] Y;
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//input
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input [31:0] A;
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input [31:0] B;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : nor32_gen_loop
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nor nor_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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// 32-bit AND
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module AND32_2x1(Y,A,B);
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//output
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output [31:0] Y;
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//input
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input [31:0] A;
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input [31:0] B;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : and32_gen_loop
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and and_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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// 32-bit inverter
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module INV32_1x1(Y,A);
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//output
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output [31:0] Y;
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//input
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input [31:0] A;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : inv32_gen_loop
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not inv32_inst(Y[i], A[i]);
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end
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endgenerate
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endmodule
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// 32-bit OR
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module OR32_2x1(Y,A,B);
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//output
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output [31:0] Y;
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//input
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input [31:0] A;
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input [31:0] B;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : or32_gen_loop
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or or32_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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// 32-bit buffer
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module BUF32_1x1(Y,A);
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//output
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output [31:0] Y;
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//input
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input [31:0] A;
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : buf32_gen_loop
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buf buf32_inst(Y[i], A[i]);
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end
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endgenerate
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endmodule
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