44 lines
1.7 KiB
Verilog
44 lines
1.7 KiB
Verilog
// Name: da_vinci.v
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// Module: DA_VINCI
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//
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// Outputs are for testbench observations only
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//
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// Output: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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// READ : Read signal
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// WRITE: Write signal
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - 32 bit bareminimum computer system DA_VINCI_v1.0 implementing cs147sec05 instruction set
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module DA_VINCI (MEM_DATA_OUT, MEM_DATA_IN, ADDR, READ, WRITE, CLK, RST);
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// Parameter for the memory initialization file name
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parameter mem_init_file = "mem_content_01.dat";
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// output list
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output [`ADDRESS_INDEX_LIMIT:0] ADDR;
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output [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
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output READ, WRITE;
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// input list
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input CLK, RST;
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// Instance section
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// Processor instanceIN
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PROC_CS147_SEC05 processor_inst(.DATA_IN(MEM_DATA_OUT), .DATA_OUT(MEM_DATA_IN),
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.ADDR(ADDR), .READ(READ),
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.WRITE(WRITE), .CLK(CLK), .RST(RST));
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// memory instance
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defparam memory_inst.mem_init_file = mem_init_file;
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MEMORY_WRAPPER memory_inst(.DATA_OUT(MEM_DATA_OUT), .DATA_IN(MEM_DATA_IN),
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.READ(READ), .WRITE(WRITE),
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.ADDR(ADDR), .CLK(CLK), .RST(RST));
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endmodule; |