47 lines
1.2 KiB
Verilog
47 lines
1.2 KiB
Verilog
// Name: rc_add_sub_32_tb.v
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// Module: RC_ADD_SUB_32_TB
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//
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// Notes: - Testbench for RC adder/asubtractor
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module RC_ADD_SUB_32_TB;
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// driver
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reg [`DATA_INDEX_LIMIT:0] A;
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reg [`DATA_INDEX_LIMIT:0] B;
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reg SnA;
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// outputs to observe
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wire CO;
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wire [`DATA_INDEX_LIMIT:0] Y;
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integer i;
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reg [`DATA_INDEX_LIMIT:0] result[0:4];
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RC_ADD_SUB_32 rc_add_sub_inst(.Y(Y), .CO(CO), .A(A), .B(B), .SnA(SnA));
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initial
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begin
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i=0;
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A=10; B=20; SnA=1'b0; // Y = 10 + 20 = 30
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#1 result[i] = Y; i=i+1;
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#1 A=10; B=20; SnA=1'b1; // Y = 10 - 20 = -10
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#1 result[i] = Y; i=i+1;
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#1 A=15; B=12; SnA=1'b1; // Y = 15 - 12 = 3
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#1 result[i] = Y; i=i+1;
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#1 A=0; B=4; SnA=1'b0; // Y = 0 + 4 = 4
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#1 result[i] = Y; i=i+1;
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#1 A=32'h80001234; B=32'h80004321; SnA=1'b0;
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#1 result[i] = Y; i=i+1;
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#1
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$writememh("./OUTPUT/rc_add_sub_32.out",result);
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$stop;
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end
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endmodule
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