112 lines
3.1 KiB
Verilog
112 lines
3.1 KiB
Verilog
// Name: proj_2_tb.v
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// Module: DA_VINCI_TB
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//
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//
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// Monitors: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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// READ : Read signal
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// WRITE: Write signal
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - Testbench for MEMORY_64MB memory system
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module MEM_64MB_TB;
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// Storage list
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reg [`ADDRESS_INDEX_LIMIT:0] ADDR;
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// reset
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reg READ, WRITE, RST;
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// data register
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reg [`DATA_INDEX_LIMIT:0] DATA_REG;
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integer i; // index for memory operation
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integer no_of_test, no_of_pass;
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integer load_data;
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// wire lists
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wire CLK;
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wire [`DATA_INDEX_LIMIT:0] DATA;
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assign DATA = ((READ===1'b0)&&(WRITE===1'b1))?DATA_REG:{`DATA_WIDTH{1'bz} };
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// Clock generator instance
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CLK_GENERATOR clk_gen_inst(.CLK(CLK));
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// 64MB memory instance
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defparam mem_inst.mem_init_file = "mem_content_01.dat";
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MEMORY_64MB mem_inst(.DATA(DATA), .ADDR(ADDR), .READ(READ),
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.WRITE(WRITE), .CLK(CLK), .RST(RST));
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initial
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begin
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RST=1'b1;
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READ=1'b0;
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WRITE=1'b0;
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DATA_REG = {`DATA_WIDTH{1'b0} };
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no_of_test = 0;
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no_of_pass = 0;
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load_data = 'h00414020;
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// Start the operation
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#10 RST=1'b0;
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#10 RST=1'b1;
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// Write cycle
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for(i=1;i<10; i = i + 1)
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begin
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#10 DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR = i;
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end
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// Read Cycle
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#10 READ=1'b0; WRITE=1'b0;
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#5 no_of_test = no_of_test + 1;
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if (DATA !== {`DATA_WIDTH{1'bz}})
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$write("[TEST] Read %1b, Write %1b, expecting 32'hzzzzzzzz, got %8h [FAILED]\n", READ, WRITE, DATA);
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else
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no_of_pass = no_of_pass + 1;
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// test of write data
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for(i=0;i<10; i = i + 1)
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begin
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#5 READ=1'b1; WRITE=1'b0; ADDR = i;
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#5 no_of_test = no_of_test + 1;
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if (DATA !== i)
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$write("[TEST] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", READ, WRITE, i, DATA);
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else
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no_of_pass = no_of_pass + 1;
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end
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// test for the initialize data
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for(i='h001000; i<'h001010; i = i + 1)
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begin
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#5 READ=1'b1; WRITE=1'b0; ADDR = i;
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#5 no_of_test = no_of_test + 1;
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if (DATA !== load_data)
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$write("[TEST] Read %1b, Write %1b, Addr %7h, expecting %8h, got %8h [FAILED]\n",
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READ, WRITE, ADDR, load_data, DATA);
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else
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no_of_pass = no_of_pass + 1;
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load_data = load_data + 1;
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end
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#10 READ=1'b0; WRITE=1'b0; // No op
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#10 $write("\n");
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$write("\tTotal number of tests %d\n", no_of_test);
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$write("\tTotal number of pass %d\n", no_of_pass);
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$write("\n");
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$writememh("./OUTPUT/mem_dump_01.dat", mem_inst.sram_32x64m, 'h0000000, 'h000000f);
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$writememh("./OUTPUT/mem_dump_02.dat", mem_inst.sram_32x64m, 'h0001000, 'h000100f);
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$stop;
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end
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endmodule;
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