144 lines
3.0 KiB
Verilog
144 lines
3.0 KiB
Verilog
// Name: logic_32_bit_tb.v
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// Module: NOR32_2x1_TB
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// AND32_2x1_TB
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// INV32_1x1_TB
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// OR32_2x1_TB
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//
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// Notes: - Testbench for shift module
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module NOR32_2x1_TB;
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//Driver
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reg [31:0] A, B;
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// Obsrver
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wire [31:0] Y;
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// result
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integer i;
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reg [31:0] result [0:4];
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NOR32_2x1 nor32_2x1_inst(.Y(Y), .A(A), .B(B));
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initial
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begin
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i=0;
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A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'h00000000; B=32'h00000000; // Y=32'hFFFFFFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'h0000FFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'hFFFF0000
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#1 result[i] = Y; i=i+1;
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#1
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$writememh("./OUTPUT/NOR32_2x1_TB.out",result);
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$stop;
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end
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endmodule
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module AND32_2x1_TB;
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//Driver
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reg [31:0] A, B;
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// Obsrver
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wire [31:0] Y;
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// result
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integer i;
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reg [31:0] result [0:4];
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AND32_2x1 and32_2x1_inst(.Y(Y), .A(A), .B(B));
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initial
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begin
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i=0;
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A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
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#1 result[i] = Y; i=i+1;
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#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
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#1 result[i] = Y; i=i+1;
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#1
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$writememh("./OUTPUT/AND32_2x1_TB.out",result);
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$stop;
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end
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endmodule
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module INV32_1x1_TB;
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//Driver
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reg [31:0] A;
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// Obsrver
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wire [31:0] Y;
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// result
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integer i;
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reg [31:0] result [0:4];
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INV32_1x1 inv32_1x1_inst(.Y(Y), .A(A));
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initial
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begin
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i=0;
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A=32'hFFFF0000; // Y = 32'h0000FFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'h00000000; // Y=32'hFFFFFFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'hA5A5A5A5; // Y = 32'h5A5A5A5A
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#1 result[i] = Y; i=i+1;
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#1 A=32'hFFFF0000; // Y = 32'h0000FFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'h0000FFFF; // Y = 32'hFFFF0000
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#1 result[i] = Y; i=i+1;
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#1
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$writememh("./OUTPUT/INV32_1x1_TB.out",result);
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$stop;
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end
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endmodule
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module OR32_2x1_TB;
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//Driver
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reg [31:0] A, B;
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// Obsrver
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wire [31:0] Y;
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// result
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integer i;
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reg [31:0] result [0:4];
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OR32_2x1 or32_2x1_inst(.Y(Y), .A(A), .B(B));
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initial
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begin
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i=0;
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A=32'hFFFF0000; B=32'h0000FFFF; // Y = 32'hFFFFFFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'h00000000; B=32'h00000000; // Y=32'h00000000
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#1 result[i] = Y; i=i+1;
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#1 A=32'hA5A5A5A5; B=32'h5A5A5A5A; // Y = 32'hFFFFFFFF
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#1 result[i] = Y; i=i+1;
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#1 A=32'hFFFF0000; B=32'hFFFF0000; // Y = 32'hFFFF0000
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#1 result[i] = Y; i=i+1;
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#1 A=32'h0000FFFF; B=32'h0000FFFF; // Y = 32'h0000FFFF
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#1 result[i] = Y; i=i+1;
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#1
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$writememh("./OUTPUT/OR32_2x1_TB.out",result);
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$stop;
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end
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endmodule |