42 lines
897 B
Verilog
42 lines
897 B
Verilog
// Name: half_adder_tb.v
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// Module: HALF_ADDER_TB
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//
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// Notes: - Testbench for half adder
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module HALF_ADDER_TB;
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reg A, B;
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wire Y, C;
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reg [`DATA_INDEX_LIMIT:0] results[0:3];
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HALF_ADDER ha_inst(.Y(Y), .C(C), .A(A), .B(B));
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initial
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begin
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A=1'b0; B=1'b0;
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#1 results[0] = 32'h00000000 | {C,Y};
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#1 A=1'b0; B=1'b1;
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#1 results[1] = 32'h00000000 | {C,Y};
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#1 A=1'b1; B=1'b0;
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#1 results[2] = 32'h00000000 | {C,Y};
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#1 A=1'b1; B=1'b1;
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#1 results[3] = 32'h00000000 | {C,Y};
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#5
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$writememh("./OUTPUT/half_adder.out",results,0,3);
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$stop;
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end
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endmodule
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