41 lines
844 B
Verilog
41 lines
844 B
Verilog
// Name: full_adder_tb.v
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// Module: FULL_ADDER_TB
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//
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// Notes: - Testbench for full adder
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module FULL_ADDER_TB;
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reg A, B, CI;
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wire S, CO;
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reg [`DATA_INDEX_LIMIT:0] result[0:7];
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integer i;
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FULL_ADDER fa_inst(.S(S), .CO(CO), .A(A), .B(B), .CI(CI));
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initial
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begin
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A=0; B=0; CI=0;
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#1 result[0] = 32'h00000000 | {CO,S};
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for(i=1; i<8; i=i+1)
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begin
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#1 CI=i[2]; A=i[1]; B=i[0];
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#1 result[i] = 32'h00000000 | {CO,S};
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end
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#1
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$writememh("./OUTPUT/full_adder.out",result);
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$stop;
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end
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endmodule
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