156 lines
4.8 KiB
Verilog
156 lines
4.8 KiB
Verilog
// Name: da_vinci_tb.v
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// Module: DA_VINCI_TB
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//
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// Outputs are for testbench observations only
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//
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// Monitors: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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// READ : Read signal
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// WRITE: Write signal
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - Testbench for DA_VINCI system
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module DA_VINCI_TB;
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// output list
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wire [`ADDRESS_INDEX_LIMIT:0] ADDR;
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wire READ, WRITE, CLK;
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// inout list
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wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
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// reset
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reg RST;
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integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
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//integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
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// Clock generator instance
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CLK_GENERATOR clk_gen_inst(.CLK(CLK));
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// DA_VINCI v1.0 instance
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defparam da_vinci_inst.mem_init_file = "./TESTPROGRAM/fibonacci.dat";
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//defparam da_vinci_inst.mem_init_file = "RevFib.dat";
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DA_VINCI da_vinci_inst(.MEM_DATA_OUT(MEM_DATA_OUT),
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.MEM_DATA_IN(MEM_DATA_IN),
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.ADDR(ADDR), .READ(READ),
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.WRITE(WRITE), .CLK(CLK), .RST(RST));
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initial
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begin
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RST=1'b1;
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if (t1 === 1)
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begin
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/* START : test 1*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating fibonacci.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/fibonacci.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#5000 $write("\n");
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$write("===> Done simulating fibonacci.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00040000, 'h0004000f);
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/* END : test 1*/
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end
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if (t2 === 1)
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begin
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/* START : test 2*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating RevFib.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/RevFib.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#5000 $write("\n");
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$write("===> Done simulating RevFib.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 'h0f, `INIT_STACK_POINTER);
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/* END : test 2*/
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end
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if (t3 === 1)
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begin
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/* START : test 3*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating CS147_SP17_HW01_02.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/CS147_SP17_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#5000 $write("\n");
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$write("===> Done simulating CS147_SP17_HW01_02.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h0004800A);
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/* END : test 3*/
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end
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if (t4 === 1)
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begin
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/* START : test 4*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating CS147_FL15_HW01_02.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/CS147_FL15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#6000 $write("\n");
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$write("===> Done simulating CS147_FL15_HW01_02.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 9, `INIT_STACK_POINTER);
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/* END : test 4*/
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end
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if (t5 === 1)
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begin
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/* START : test 5*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating CS147_SP15_HW01_02.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/CS147_SP15_HW01_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#5000 $write("\n");
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$write("===> Done simulating CS147_SP15_HW01_02.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048005);
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$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
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/* END : test 5*/
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end
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if (t6 === 1)
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begin
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/* START : test 6*/
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#5 RST=1'b0;
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#5 RST=1'b1;
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$write("\n");
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$write("===> Simulating all_test.dat\n", "");
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$write("\n");
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$readmemh("./TESTPROGRAM/all_test.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m);
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#5000 $write("\n");
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$write("===> Done simulating all_test.dat\n", "");
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$write("\n");
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$writememh("./OUTPUT/all_test_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048011);
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$writememh("./OUTPUT/all_test_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
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/* END : test 6*/
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end
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$stop;
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end
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endmodule;
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