81 lines
1.5 KiB
Verilog
81 lines
1.5 KiB
Verilog
// Name: barrel_shifter_tb.v
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// Module: BARREL_SHIFTER32_TB
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//
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// Notes: - Testbench for shift module
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module BARREL_SHIFTER32_TB;
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reg [31:0] D;
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reg [31:0] S;
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reg LnR;
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wire [31:0] Y;
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integer reg_idx;
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reg [`DATA_INDEX_LIMIT:0] result[0:63];
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integer i, e;
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integer no_of_test=0;
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integer no_of_pass=0;
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SHIFT32 shift_inst(.Y(Y), .D(D), .S(S), .LnR(LnR));
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initial
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begin
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reg_idx=0;
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D=32'ha5a5a5a5;
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S=32'h00000000;
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LnR=1'b1; // left shift
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for(i=1; i<33; i=i+1)
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begin
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#5
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no_of_test = no_of_test + 1;
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S=i;
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e = D << S;
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#5
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if (e !== Y)
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begin
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$write("[TEST %2d] (%8x << %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
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end
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else
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no_of_pass = no_of_pass + 1;
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result[reg_idx] = Y; reg_idx=reg_idx+1;
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end
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#5 LnR=1'b0; // right shift
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for(i=1; i<33; i=i+1)
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begin
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#5
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no_of_test = no_of_test + 1;
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S=i;
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e = D >> S;
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#5
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if (e !== Y)
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begin
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$write("[TEST %2d] (%8x >> %8x) = %8x, got %8x ... FAILED\n", no_of_test, D, S, e, Y);
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end
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else
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no_of_pass = no_of_pass + 1;
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result[reg_idx] = Y; reg_idx=reg_idx+1;
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end
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$write("\n");
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$write("\tTotal number of tests %d\n", no_of_test);
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$write("\tTotal number of pass %d\n", no_of_pass);
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$write("\n");
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$writememh("./OUTPUT/barret_shifter_tb.out",result);
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$stop;
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end
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endmodule
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