86 lines
2.3 KiB
Verilog
86 lines
2.3 KiB
Verilog
// Name: alu_tb.v
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// Module: ALU_TB
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//
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// Notes: - Testbench for ALU
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "../prj_definition.v"
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module ALU_TB;
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// reg list
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reg [`DATA_INDEX_LIMIT:0] OP1; // operand 1
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reg [`DATA_INDEX_LIMIT:0] OP2; // operand 2
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reg [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
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// output list
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wire [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
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wire ZERO;
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// results
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integer ridx;
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reg [`DATA_INDEX_LIMIT:0] result[199:0];
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// Testcases
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integer oprnd_idx, oprn_idx;
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integer NumSet01[0:7];
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integer NumSet02[0:7];
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integer OpCode[0:8];
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ALU alu_inst(.OUT(OUT), .ZERO(ZERO), .OP1(OP1), .OP2(OP2), .OPRN(OPRN));
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initial
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begin
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// Initialize number sets
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NumSet01[0] = 10; NumSet01[1] = -15; NumSet01[2] = 25; NumSet01[3] = -30; NumSet01[4] = 0; NumSet01[5] = -15; NumSet01[6] = 23; NumSet01[7] = 0;
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NumSet02[0] = 10; NumSet02[1] = 15; NumSet02[2] = -25; NumSet02[3] = -30; NumSet02[4] = 0; NumSet02[5] = 42; NumSet02[6] = 0; NumSet02[7] = 70;
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ridx = 0;
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// Set of operation
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OpCode[0] = 1; // add
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OpCode[1] = 2; // sub
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OpCode[2] = 3; // mult
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OpCode[3] = 4; // shiftR
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OpCode[4] = 5; // shiftL
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OpCode[5] = 6; // and
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OpCode[6] = 7; // or
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OpCode[7] = 8; // nor
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OpCode[8] = 9; // slt
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// Loop through operands and operation
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for(oprnd_idx=0; oprnd_idx<8; oprnd_idx=oprnd_idx+1)
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begin
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for(oprn_idx=0; oprn_idx<9; oprn_idx=oprn_idx+1)
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begin
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#1 OP1=NumSet01[oprnd_idx]; OP2=NumSet02[oprnd_idx]; OPRN=OpCode[oprn_idx];
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#1
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$write("===> %0d ",$signed(OP1));
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case(OPRN)
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1: $write("+");
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2: $write("-");
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3: $write("*");
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4: $write(">>");
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5: $write("<<");
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6: $write("&");
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7: $write("|");
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8: $write("|~");
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9: $write("slt");
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endcase
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$write(" %0d = %0d [%d]\n", $signed(OP2), $signed(OUT), ZERO);
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result[ridx] = OUT; ridx = ridx + 1;
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result[ridx] = ZERO; ridx = ridx + 1;
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end
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end
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#1
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$writememh("./OUTPUT/alu_tb.out", result, 0, (ridx-1));
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$stop;
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end
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endmodule
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