implement a Verilog gate level model for ripple carry adder subtractor

Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32

full_adder.v

@@ -23,6 +23,9 @@ module FULL_ADDER(S,CO,A,B, CI);
 output S,CO;
 input A,B, CI;
 
-//TBD
+wire Y, CO1, CO2;
+HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
+HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
+or (CO, CO1, CO2);
 
-endmodule;
+endmodule

half_adder.v

@@ -22,6 +22,7 @@ module HALF_ADDER(Y,C,A,B);
 output Y,C;
 input A,B;
 
-// TBD
+xor digit(Y, A, B);
+and carry(C, A, B);
 
-endmodule;
+endmodule

rc_add_sub_32.v

@@ -42,7 +42,19 @@ input [`DATA_INDEX_LIMIT:0] A;
 input [`DATA_INDEX_LIMIT:0] B;
 input SnA;
 
-// TBD
+// carry-in bits for each 1-bit full adder
+wire C[0:32];
+buf (C[0], SnA);
+
+genvar i;
+generate
+    for (i = 0; i < 32; i = i + 1)
+    begin : add32_gen_loop
+        FULL_ADDER add_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
+    end
+endgenerate
+
+//assign CO = C[32];
+buf (CO, C[32]);
 
 endmodule
-