WIP: failed attempt to use many-input or gates

TESTBENCH/barrel_shifter_tb.v

@@ -18,7 +18,7 @@ reg LnR;
 wire [31:0] Y;
 
 integer reg_idx;
-reg [`DATA_INDEX_LIMIT:0] result[0:63];
+reg [`DATA_INDEX_LIMIT:0] result[0:123];
 
 integer i, e;
 integer no_of_test=0;
@@ -33,7 +33,7 @@ D=32'ha5a5a5a5;
 S=32'h00000000;
 LnR=1'b1; // left shift
 
-for(i=1; i<33; i=i+1)
+for(i=1; i<63; i=i+1)
 begin
 #5 
 no_of_test = no_of_test + 1;
@@ -51,7 +51,7 @@ end
 
 #5 LnR=1'b0; // right shift
 
-for(i=1; i<33; i=i+1)
+for(i=1; i<63; i=i+1)
 begin
 #5 
 no_of_test = no_of_test + 1;

TESTBENCH/register_file_tb.v

@@ -68,52 +68,24 @@ no_of_pass = 0;
 // Write cycle
 for(i=0;i<32; i = i + 1)
 begin
-#10     DATA_REG = i * 10; READ=1'b0; WRITE=1'b1; ADDR_W = i;
+#10     DATA_REG=i; READ=1'b0; WRITE=1'b1; ADDR_W = i;
 end
 
 #5 READ=1'b0; WRITE=1'b0;
 // test of write data
 for(i=0;i<32; i = i + 1)
 begin
-#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i % 7;
+#5      READ=1'b1; WRITE=1'b0; ADDR_R1 = i; ADDR_R2 = i;
 #5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== i * 10)
+        if (DATA_R1 !== i)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 10, DATA_R1);
+	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i, DATA_R1);
-        else if (DATA_R2 !== (i % 7) * 10)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, (i % 7) * 10, DATA_R2);
         else 
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
+        result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
-// Testing read and write at the same time
-for(i=2;i<16; i = i + 1)
-begin
-#5      DATA_REG = 20; READ=1'b1; WRITE=1'b1; ADDR_W = i + 1; ADDR_R1 = i; ADDR_R2 = i * 2;
-#5      no_of_test = no_of_test + 1;
-        if (DATA_R1 !== 20)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, 20, DATA_R1);
-        else if (DATA_R2 !== i * 20)
-	    $write("[TEST @ %0dns] Read %1b, Write %1b, expecting %8h, got %8h [FAILED]\n", $time, READ, WRITE, i * 20, DATA_R2);
-        else
-	    no_of_pass  = no_of_pass + 1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
-
-end
-
-// Test reading when READ=0
-#5     READ=1'b0;
-#5     no_of_test = no_of_test + 1;
-if (DATA_R1 !== 32'bx)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
-else if (DATA_R2 !== 32'bx)
-        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
-else
-no_of_pass  = no_of_pass + 1;
-result[ridx] = DATA_R1; ridx=ridx+1;
-
-// TODO: Read and write from the same address at the same time?
 
 #5    READ=1'b0; WRITE=1'b0; // No op
 

alu.v

@@ -31,11 +31,12 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;
 
-wire [31:0] res,
+wire [31:0] //res,
             res_addsub, res_slt,
             res_shift,
             res_mul,
             res_and, res_or, res_nor;
+wire [31:0] res;
 
 // add = xx0001
 // sub = xx0010
@@ -71,16 +72,10 @@ MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
 );
 
 // or bits of result for zero flag
-wire nzf [31:0];
+wire nzf;
-buf (nzf[0], res[0]);
+or (nzf, res[24:0]);
-genvar i;
-generate
-    for (i = 1; i < 32; i = i + 1) begin : zf_gen
-        or (nzf[i], nzf[i-1], res[i]);
-    end
-endgenerate
 
-not (ZERO, nzf[31]);
+not (ZERO, nzf);
 buf res_out [31:0] (OUT, res);
 
 endmodule

barrel_shifter.v

@@ -22,20 +22,14 @@ input [31:0] S;
 input LnR;
 
 // check if upper bits are nonzero
-wire oob [31:5];
+wire oob;
-buf (oob[5], S[5]);
+or (oob, S[31:5]);
-genvar i;
-generate
-    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
-        or (oob[i], oob[i-1], S[i]);
-    end
-endgenerate
 
 wire [31:0] shifted;
 BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
 
 // return 0 if S >= 32
-MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
+MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob);
 
 endmodule
 

logic.v

@@ -43,12 +43,7 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-genvar i;
+// TBD
-generate
-    for (i = 0; i < 32; i = i + 1) begin : reg_gen
-        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
-    end
-endgenerate
 
 endmodule
 
@@ -61,10 +56,7 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;
 
-wire D_out;
+// TBD
-MUX1_2x1 data(D_out, Q, D, L);
-
-D_FF dff(Q, Qbar, D_out, C, nP, nR);
 
 endmodule
 
@@ -77,11 +69,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-wire Cbar, Y, Ybar;
+// TBD
-not C_inv(Cbar, C);
-D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
-
-SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
 
 endmodule
 
@@ -94,10 +82,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-wire Dbar;
+// TBD
-not D_inv(Dbar, D);
-
-SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
 
 endmodule
 
@@ -110,13 +95,7 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;
 
-wire r1, r2;
+// TBD
-
-nand n1(r1, C, S);
-nand n2(r2, C, R);
-
-nand n3(Q, nP, r1, Qbar);
-nand n4(Qbar, nR, r2, Q);
 
 endmodule
 
@@ -127,19 +106,7 @@ output [31:0] D;
 // input
 input [4:0] I;
 
-wire [15:0] half;
+// TBD
-wire I_not;
-not I_inv(I_not, I[4]);
-
-DECODER_4x16 d(half, I[3:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 16; i = i + 1) begin : d5_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 16], I[4], half[i]);
-    end
-endgenerate
 
 endmodule
 
@@ -150,19 +117,7 @@ output [15:0] D;
 // input
 input [3:0] I;
 
-wire [7:0] half;
+// TBD
-wire I_not;
-not I_inv(I_not, I[3]);
-
-DECODER_3x8 d(half, I[2:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 8; i = i + 1) begin : d4_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 8], I[3], half[i]);
-    end
-endgenerate
 
 
 endmodule
@@ -174,19 +129,8 @@ output [7:0] D;
 // input
 input [2:0] I;
 
-wire [3:0] half;
+//TBD
-wire I_not;
-not I_inv(I_not, I[2]);
 
-DECODER_2x4 d(half, I[1:0]);
-
-genvar i;
-generate
-    for (i = 0; i < 4; i = i + 1) begin : d3_gen
-        and msb0(D[i], I_not, half[i]);
-        and msb1(D[i + 4], I[2], half[i]);
-    end
-endgenerate
 
 endmodule
 

mux.v

@@ -27,16 +27,7 @@ input [31:0] I16, I17, I18, I19, I20, I21, I22, I23;
 input [31:0] I24, I25, I26, I27, I28, I29, I30, I31;
 input [4:0] S;
 
-wire [31:0] x0, x1;
+// TBD
-MUX32_16x1 mux16_0(x0, I0, I1, I2, I3, I4, I5, I6, I7,
-                       I8, I9, I10, I11, I12, I13, I14, I15,
-                       S[3:0]
-);
-MUX32_16x1 mux16_1(x1, I16, I17, I18, I19, I20, I21, I22, I23,
-                       I24, I25, I26, I27, I28, I29, I30, I31,
-                       S[3:0]
-);
-MUX32_2x1 out(Y, x0, x1, S[4]);
 
 endmodule
 

register_file.v

@@ -41,27 +41,6 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-wire [31:0] Q [31:0];
+// TBD
-wire [31:0] r_write;
-DECODER_5x32 d_write(r_write, ADDR_W);
-
-REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
-
-wire [31:0] r1, r2;
-MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
-                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
-                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
-                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
-                     ADDR_R1
-);
-MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
-                     Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
-                     Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
-                     Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
-                     ADDR_R2
-);
-
-MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
-MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
 
 endmodule