misc: fix unconnected port warnings for ALU and TWOSCOMP

TESTBENCH/register_file_tb.v

@@ -84,7 +84,6 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
         
 end
 
@@ -100,11 +99,22 @@ begin
         else
 	    no_of_pass  = no_of_pass + 1;
         result[ridx] = DATA_R1; ridx=ridx+1;
-        result[ridx] = DATA_R1; ridx=ridx+1;
 
 end
 
+// Test reading when READ=0
+#5     READ=1'b0;
+#5     no_of_test = no_of_test + 1;
+if (DATA_R1 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R1 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R1);
+else if (DATA_R2 !== 32'bx)
+        $write("[TEST @ %0dns] READ=0, expecting DATA_R2 to be 32{x}, got %8h [FAILED]\n", $time, DATA_R2);
+else
+no_of_pass  = no_of_pass + 1;
+result[ridx] = DATA_R1; ridx=ridx+1;
+
 // TODO: Read and write from the same address at the same time?
+// TODO: Write when WRITE=0 should be tested
 
 #5    READ=1'b0; WRITE=1'b0; // No op
 

alu.v

@@ -44,7 +44,7 @@ wire [31:0] res,
 // can use oprn[1] or oprn[3] for SnA
 wire SnA;
 or (SnA, OPRN[1], OPRN[3]);
-RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
+RC_ADD_SUB_32 addsub(.Y(res_addsub), .CO(), .A(OP1), .B(OP2), .SnA(SnA));
 buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
 
 // shift_r = xx0100
@@ -54,7 +54,7 @@ buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
 SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
 
 // mul = xx0011
-MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
+MULT32 mul(.LO(res_mul), .HI(), .A(OP1), .B(OP2));
 
 // and = xx0110
 // or  = xx0111
@@ -63,11 +63,12 @@ AND32_2x1 and32(res_and, OP1, OP2);
 OR32_2x1 or32(res_or, OP1, OP2);
 NOR32_2x1 nor32(res_nor, OP1, OP2);
 
-MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
+MUX32_16x1 out(.Y(res), .S(OPRN[3:0]), .I0(),
                .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
                .I4(res_shift),.I5(res_shift),
                .I6(res_and), .I7(res_or), .I8(res_nor),
-               .I9(res_slt)
+               .I9(res_slt),
+               .I10(), .I11(), .I12(), .I13(), .I14(), .I15()
 );
 
 // or bits of result for zero flag

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(), .A(64'b0), .B(A), .SnA(1'b1));
 
 endmodule
 
@@ -31,7 +31,31 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
+RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(), .A(0), .B(A), .SnA(1'b1));
+
+endmodule
+
+// 32-bit register with parameterized preset pattern
+module REG32_PP(Q, D, LOAD, CLK, RESET);
+parameter PATTERN = 32'h00000000;
+output [31:0] Q;
+
+input CLK, LOAD;
+input [31:0] D;
+input RESET;
+
+wire [31:0] qbar;
+
+genvar i;
+generate
+    for(i=0; i<32; i=i+1)
+    begin : reg32_gen_loop
+       if (PATTERN[i] == 0)
+              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(1'b1), .nR(RESET));
+        else
+              REG1 reg_inst(.Q(Q[i]), .Qbar(qbar[i]), .D(D[i]), .L(LOAD), .C(CLK), .nP(RESET), .nR(1'b1));
+    end
+endgenerate
 
 endmodule
 

register_file.v

@@ -41,31 +41,30 @@ input [`REG_ADDR_INDEX_LIMIT:0] ADDR_R1, ADDR_R2, ADDR_W;
 output [`DATA_INDEX_LIMIT:0] DATA_R1;
 output [`DATA_INDEX_LIMIT:0] DATA_R2;
 
-// module REG32(Q, D, LOAD, CLK, RESET);
-// module DECODER_5x32(D,I);
-
-// module MUX32_32x1(Y, I0, I1, I2, I3, I4, I5, I6, I7,
-                     // I8, I9, I10, I11, I12, I13, I14, I15,
-                     // I16, I17, I18, I19, I20, I21, I22, I23,
-                     // I24, I25, I26, I27, I28, I29, I30, I31, S);
-
 wire [31:0] Q [31:0];
-wire [31:0] write;
-DECODER_5x32 d_write(write, ADDR_W);
+wire [31:0] r_write_sel, r_write;
+DECODER_5x32 d_write(r_write_sel, ADDR_W);
 
-REG32 r[31:0] (Q, DATA_W, write, CLK, RST);
+// only write when WRITE=1
+and write_active [31:0] (r_write, r_write_sel, WRITE);
 
-MUX32_32x1 r1(DATA_R1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+REG32 r[31:0] (Q, DATA_W, r_write, CLK, RST);
+
+wire [31:0] r1, r2;
+MUX32_32x1 mux_r1(r1, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R1
 );
-MUX32_32x1 r2(DATA_R2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
+MUX32_32x1 mux_r2(r2, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7],
                      Q[8], Q[9], Q[10], Q[11], Q[12], Q[13], Q[14], Q[15],
                      Q[16], Q[17], Q[18], Q[19], Q[20], Q[21], Q[22], Q[23],
                      Q[24], Q[25], Q[26], Q[27], Q[28], Q[29], Q[30], Q[31],
                      ADDR_R2
 );
 
+MUX32_2x1 mux_out1(DATA_R1, {32{1'bZ}}, r1, READ);
+MUX32_2x1 mux_out2(DATA_R2, {32{1'bZ}}, r2, READ);
+
 endmodule