implement a Verilog gate level model for ripple carry adder subtractor

Gate level implementation for the following components:
- FULL_ADDER
- HALF_ADDER
- RC_ADD_SUB_32

TESTBENCH/mult_tb.v

@@ -36,8 +36,6 @@ A=10; B=20;     // Y = 10 * 20 = 200
 #1 result[i] = {HI,LO}; i=i+1;
 #1 A=10; B=19; 	// Y = 10 * 19 = 190
 #1 result[i] = {HI,LO}; i=i+1;
-#1 A=32'h00d96027; B=32'h7c32b43c; 	// Y = 0x0d96027 * 0x7c32b43c = 0x 006975a0 b62bf524
-#1 result[i] = {HI,LO}; i=i+1;
 #1 A=32'h70000000; B=32'h70000000; 
 #1 result[i] = {HI,LO}; i=i+1;
 #1 

alu.v

@@ -31,56 +31,7 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
 output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
 output ZERO;
 
-wire [31:0] res,
+// TBD
-            res_addsub, res_slt,
-            res_shift,
-            res_mul,
-            res_and, res_or, res_nor;
 
-// add = xx0001
-// sub = xx0010
-// slt = xx1001
-//         ^ ^ these bits
-// can use oprn[1] or oprn[3] for SnA
-wire SnA;
-or (SnA, OPRN[1], OPRN[3]);
-RC_ADD_SUB_32 addsub(.Y(res_addsub), .A(OP1), .B(OP2), .SnA(SnA));
-buf slt [31:0] (res_slt, {31'b0,res_addsub[31]});
-
-// shift_r = xx0100
-// shift_l = xx0101
-//                ^ this bit
-// can use oprn[0] for LnR
-SHIFT32 shift(res_shift, OP1, OP2, OPRN[0]);
-
-// mul = xx0011
-MULT32 mul(.LO(res_mul), .A(OP1), .B(OP2));
-
-// and = xx0110
-// or  = xx0111
-// nor = xx1000
-AND32_2x1 and32(res_and, OP1, OP2);
-OR32_2x1 or32(res_or, OP1, OP2);
-NOR32_2x1 nor32(res_nor, OP1, OP2);
-
-MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
-               .I1(res_addsub), .I2(res_addsub), .I3(res_mul),
-               .I4(res_shift),.I5(res_shift),
-               .I6(res_and), .I7(res_or), .I8(res_nor),
-               .I9(res_slt)
-);
-
-// or bits of result for zero flag
-wire nzf [31:0];
-buf (nzf[0], res[0]);
-genvar i;
-generate
-    for (i = 1; i < 32; i = i + 1) begin : zf_gen
-        or (nzf[i], nzf[i-1], res[i]);
-    end
-endgenerate
-
-not (ZERO, nzf[31]);
-buf res_out [31:0] (OUT, res);
 
 endmodule

barrel_shifter.v

@@ -21,21 +21,7 @@ input [31:0] D;
 input [31:0] S;
 input LnR;
 
-// check if upper bits are nonzero
+// TBD
-wire oob [31:5];
-buf (oob[5], S[5]);
-genvar i;
-generate
-    for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
-        or (oob[i], oob[i-1], S[i]);
-    end
-endgenerate
-
-wire [31:0] shifted;
-BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
-
-// return 0 if S >= 32
-MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]);
 
 endmodule
 
@@ -48,11 +34,7 @@ input [31:0] D;
 input [4:0] S;
 input LnR;
 
-wire [31:0] shifters [1:0];
+// TBD
-SHIFT32_R shifter_r(shifters[0], D, S);
-SHIFT32_L shifter_l(shifters[1], D, S);
-
-MUX32_2x1 mux_lnr(Y, shifters[0], shifters[1], LnR);
 
 endmodule
 
@@ -64,22 +46,7 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-wire [31:0] stages [5:0];
+// TBD
-buf stage0[31:0] (stages[0], D);
-
-genvar i, j;
-generate
-    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
-        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
-            if (j < 32 - (2 ** i))
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j + (2 ** i)], S[i]);
-            else
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
-        end
-    end
-endgenerate
-
-buf out[31:0] (Y, stages[5]);
 
 endmodule
 
@@ -91,22 +58,7 @@ output [31:0] Y;
 input [31:0] D;
 input [4:0] S;
 
-
+// TBD
-wire [31:0] stages [5:0];
-buf stage0[31:0] (stages[0], D);
-
-genvar i, j;
-generate
-    for (i = 0; i < 5; i = i + 1) begin : shift_stage_gen
-        for (j = 0; j < 32; j = j + 1) begin : stage_mux_gen
-            if (j >= (2 ** i))
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], stages[i][j - (2 ** i)], S[i]);
-            else
-                MUX1_2x1 mux_stage(stages[i+1][j], stages[i][j], 1'b0, S[i]);
-        end
-    end
-endgenerate
-
-buf out[31:0] (Y, stages[5]);
 
 endmodule
+

logic.v

@@ -20,7 +20,7 @@ output [63:0] Y;
 //input list
 input [63:0] A;
 
-RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 
@@ -31,7 +31,7 @@ output [31:0] Y;
 //input list
 input [31:0] A;
 
-RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
+// TBD
 
 endmodule
 
@@ -43,12 +43,7 @@ input CLK, LOAD;
 input [31:0] D;
 input RESET;
 
-genvar i;
+// TBD
-generate
-    for (i = 0; i < 32; i = i + 1) begin : reg_gen
-        REG1 r(Q[i], _, D[i], LOAD, CLK, 1'b1, RESET);
-    end
-endgenerate
 
 endmodule
 
@@ -61,10 +56,7 @@ input D, C, L;
 input nP, nR;
 output Q,Qbar;
 
-wire D_out;
+// TBD
-MUX1_2x1 data(D_out, Q, D, L);
-
-D_FF dff(Q, Qbar, D_out, C, nP, nR);
 
 endmodule
 
@@ -77,11 +69,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-wire Cbar, Y, Ybar;
+// TBD
-not C_inv(Cbar, C);
-D_LATCH dlatch(Y, Ybar, D, Cbar, nP, nR);
-
-SR_LATCH srlatch(Q, Qbar, Y, Ybar, C, nP, nR);
 
 endmodule
 
@@ -94,10 +82,7 @@ input D, C;
 input nP, nR;
 output Q,Qbar;
 
-wire Dbar;
+// TBD
-not D_inv(Dbar, D);
-
-SR_LATCH latch(Q, Qbar, D, Dbar, C, nP, nR);
 
 endmodule
 
@@ -110,13 +95,7 @@ input S, R, C;
 input nP, nR;
 output Q,Qbar;
 
-wire r1, r2;
+// TBD
-
-nand n1(r1, C, S);
-nand n2(r2, C, R);
-
-nand n3(Q, nP, r1, Qbar);
-nand n4(Qbar, nR, r2, Q);
 
 endmodule
 
@@ -162,12 +141,6 @@ output [3:0] D;
 // input
 input [1:0] I;
 
-wire I_not [1:0];
+// TBD
-not I_inv[1:0] (I_not, I);
 
-and (D[0], I_not[1], I_not[0]);
+endmodule
-and (D[1], I_not[1], I[0]);
-and (D[2], I[1], I_not[0]);
-and (D[3], I[1], I[0]);
-
-endmodule

logic_32_bit.v

@@ -80,19 +80,3 @@ generate
     end
 endgenerate
 endmodule
-
-// 32-bit buffer
-module BUF32_1x1(Y,A);
-//output 
-output [31:0] Y;
-//input
-input [31:0] A;
-
-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1)
-    begin : buf32_gen_loop
-        buf buf32_inst(Y[i], A[i]);
-    end
-endgenerate
-endmodule

mult.v

@@ -27,25 +27,7 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;
 
-wire [31:0] A_neg, B_neg;
+// TBD
-TWOSCOMP32 A_twoscomp(A_neg, A);
-TWOSCOMP32 B_twoscomp(B_neg, B);
-
-wire [31:0] A_abs, B_abs;
-MUX32_2x1 A_mux(A_abs, A, A_neg, A[31]);
-MUX32_2x1 B_mux(B_abs, B, B_neg, B[31]);
-
-wire [31:0] HI_abs, LO_abs;
-MULT32_U mult_abs(HI_abs, LO_abs, A_abs, B_abs);
-
-wire [31:0] HI_neg, LO_neg;
-TWOSCOMP64 mult_neg({HI_neg,LO_neg}, {HI_abs,LO_abs});
-
-wire sign;
-xor (sign, A[31], B[31]);
-
-MUX32_2x1 HI_mux(HI, HI_abs, HI_neg, sign);
-MUX32_2x1 LO_mux(LO, LO_abs, LO_neg, sign);
 
 endmodule
 
@@ -57,37 +39,6 @@ output [31:0] LO;
 input [31:0] A;
 input [31:0] B;
 
-// partial sums
+// TBD
-wire [31:0] Y [31:0];
-
-// first partial is just
-AND32_2x1 partial_1(Y[0], A, {32{B[0]}});
-// put lowest bit from first partial into result
-buf (LO[0], Y[0][0]);
-
-
-// carries from partial adders
-wire CI[31:0];
-// first carry is always 0
-buf (CI[0], 0);
-
-genvar i;
-generate
-    for (i = 0; i < 31; i = i + 1)
-    begin : mult32u_gen_loop
-        // multiply A by a single digit in B
-        wire [31:0] A_and;
-        AND32_2x1 partial_and_inst(A_and, A, {32{B[i+1]}});
-
-        // calc the next partial and carry (i + 1)
-        RC_ADD_SUB_32 partial_add_inst(.Y(Y[i+1]), .CO(CI[i+1]), .A(A_and), .B({CI[i],Y[i][31:1]}), .SnA(1'b0));
-
-        // put lowest bit from calc into result
-        buf (LO[i+1], Y[i+1][0]);
-    end
-endgenerate
-
-// last carry and partial is HI
-BUF32_1x1 buf_hi(HI, {CI[31],Y[31][31:1]});
 
 endmodule

mux.v

@@ -55,11 +55,7 @@ input [31:0] I14;
 input [31:0] I15;
 input [3:0] S;
 
-
+// TBD
-wire [31:0] x0, x1;
-MUX32_8x1 mux8_0(x0, I0, I1, I2, I3, I4, I5, I6, I7, S[2:0]);
-MUX32_8x1 mux8_1(x1, I8, I9, I10, I11, I12, I13, I14, I15, S[2:0]);
-MUX32_2x1 out(Y, x0, x1, S[3]);
 
 endmodule
 
@@ -78,10 +74,7 @@ input [31:0] I6;
 input [31:0] I7;
 input [2:0] S;
 
-wire [31:0] x0, x1;
+// TBD
-MUX32_4x1 mux4_0(x0, I0, I1, I2, I3, S[1:0]);
-MUX32_4x1 mux4_1(x1, I4, I5, I6, I7, S[1:0]);
-MUX32_2x1 out(Y, x0, x1, S[2]);
 
 endmodule
 
@@ -96,10 +89,7 @@ input [31:0] I2;
 input [31:0] I3;
 input [1:0] S;
 
-wire [31:0] x0, x1;
+// TBD
-MUX32_2x1 mux2_0(x0, I0, I1, S[0]);
-MUX32_2x1 mux2_1(x1, I2, I3, S[0]);
-MUX32_2x1 out(Y, x0, x1, S[1]);
 
 endmodule
 
@@ -112,22 +102,7 @@ input [31:0] I0;
 input [31:0] I1;
 input S;
 
-// only need 1 not gate
+// TBD
-wire S_not;
-not (S_not, S);
-
-// wire [31:0] x0, x1;
-
-genvar i;
-generate
-    for (i = 0; i < 32; i = i + 1)
-    begin : mux32_gen_loop
-        wire x0, x1;
-        and (x0, S_not, I0[i]);
-        and (x1, S, I1[i]);
-        or (Y[i], x0, x1);
-    end
-endgenerate
 
 endmodule
 
@@ -138,10 +113,6 @@ output Y;
 //input list
 input I0, I1, S;
 
-wire S_not, x0, x1;
+// TBD
-not (S_not, S);
-and (x0, S_not, I0);
-and (x1, S, I1);
-or (Y, x0, x1);
 
 endmodule

rc_add_sub_32.v

@@ -29,21 +29,7 @@ input [63:0] A;
 input [63:0] B;
 input SnA;
 
-// carry-in bits for each 1-bit full adder
+// TBD
-wire C[0:64];
-buf (C[0], SnA);
-
-genvar i;
-generate
-    for (i = 0; i < 64; i = i + 1)
-    begin : add64_gen_loop
-        wire B_xor;
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
-    end
-endgenerate
-
-buf (CO, C[64]);
 
 endmodule
 
@@ -64,12 +50,11 @@ genvar i;
 generate
     for (i = 0; i < 32; i = i + 1)
     begin : add32_gen_loop
-        wire B_xor;
+        FULL_ADDER add_inst(Y[i], C[i+1], A[i], B[i] ^ SnA, C[i]);
-        xor (B_xor, B[i], SnA);
-        FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
     end
 endgenerate
 
+//assign CO = C[32];
 buf (CO, C[32]);
 
 endmodule