project: more cleanup
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@@ -30,8 +30,8 @@ wire [`DATA_INDEX_LIMIT:0] MEM_DATA_OUT, MEM_DATA_IN;
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// reset
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reg RST;
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//integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
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integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
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integer t1=1, t2=1, t3=1, t4=1, t5=1, t6=1;
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//integer t1=0, t2=0, t3=0, t4=0, t5=0, t6=1;
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// Clock generator instance
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CLK_GENERATOR clk_gen_inst(.CLK(CLK));
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