implement a Verilog gate level model for 32-bit basic logic gates
Gate level implementation for the following components: - NOR32_2x1 - AND32_2x1 - INV32_1x1 - OR32_2x1
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logic_32_bit.v
Normal file → Executable file
36
logic_32_bit.v
Normal file → Executable file
@ -22,8 +22,13 @@ output [31:0] Y;
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input [31:0] A;
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input [31:0] A;
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input [31:0] B;
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input [31:0] B;
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// TBD
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : nor32_gen_loop
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nor nor_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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endmodule
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// 32-bit AND
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// 32-bit AND
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@ -34,8 +39,13 @@ output [31:0] Y;
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input [31:0] A;
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input [31:0] A;
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input [31:0] B;
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input [31:0] B;
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// TBD
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : and32_gen_loop
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and and_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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endmodule
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// 32-bit inverter
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// 32-bit inverter
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@ -45,8 +55,13 @@ output [31:0] Y;
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//input
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//input
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input [31:0] A;
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input [31:0] A;
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// TBD
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : inv32_gen_loop
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not inv32_inst(Y[i], A[i]);
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end
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endgenerate
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endmodule
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endmodule
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// 32-bit OR
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// 32-bit OR
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@ -57,6 +72,11 @@ output [31:0] Y;
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input [31:0] A;
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input [31:0] A;
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input [31:0] B;
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input [31:0] B;
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// TBD
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : or32_gen_loop
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or or32_inst(Y[i], A[i], B[i]);
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end
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endgenerate
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endmodule
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endmodule
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