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WIP: failed attempt to use many-input or gates

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This commit is contained in:
Yuri Tatishchev 2024-10-19 15:18:51 -07:00
parent 8dbdebb9ce
commit 7bb0331226
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
3 changed files with 11 additions and 22 deletions
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6
TESTBENCH/barrel_shifter_tb.v
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@ -18,7 +18,7 @@ reg LnR;
wire [31:0] Y; wire [31:0] Y;
integer reg_idx; integer reg_idx;
reg [`DATA_INDEX_LIMIT:0] result[0:63]; reg [`DATA_INDEX_LIMIT:0] result[0:123];
integer i, e; integer i, e;
integer no_of_test=0; integer no_of_test=0;
@ -33,7 +33,7 @@ D=32'ha5a5a5a5;
S=32'h00000000; S=32'h00000000;
LnR=1'b1; // left shift LnR=1'b1; // left shift
for(i=1; i<33; i=i+1) for(i=1; i<63; i=i+1)
begin begin
#5 #5
no_of_test = no_of_test + 1; no_of_test = no_of_test + 1;
@ -51,7 +51,7 @@ end
#5 LnR=1'b0; // right shift #5 LnR=1'b0; // right shift
for(i=1; i<33; i=i+1) for(i=1; i<63; i=i+1)
begin begin
#5 #5
no_of_test = no_of_test + 1; no_of_test = no_of_test + 1;

15
alu.v
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@ -31,11 +31,12 @@ input [`ALU_OPRN_INDEX_LIMIT:0] OPRN; // operation code
output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation. output [`DATA_INDEX_LIMIT:0] OUT; // result of the operation.
output ZERO; output ZERO;
wire [31:0] res, wire [31:0] //res,
res_addsub, res_slt, res_addsub, res_slt,
res_shift, res_shift,
res_mul, res_mul,
res_and, res_or, res_nor; res_and, res_or, res_nor;
wire [31:0] res;
// add = xx0001 // add = xx0001
// sub = xx0010 // sub = xx0010
@ -71,16 +72,10 @@ MUX32_16x1 out(.Y(res), .S(OPRN[3:0]),
); );
// or bits of result for zero flag // or bits of result for zero flag
wire nzf [31:0]; wire nzf;
buf (nzf[0], res[0]); or (nzf, res[24:0]);
genvar i;
generate
for (i = 1; i < 32; i = i + 1) begin : zf_gen
or (nzf[i], nzf[i-1], res[i]);
end
endgenerate
not (ZERO, nzf[31]); not (ZERO, nzf);
buf res_out [31:0] (OUT, res); buf res_out [31:0] (OUT, res);
endmodule endmodule

12
barrel_shifter.v
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@ -22,20 +22,14 @@ input [31:0] S;
input LnR; input LnR;
// check if upper bits are nonzero // check if upper bits are nonzero
wire oob [31:5]; wire oob;
buf (oob[5], S[5]); or (oob, S[31:5]);
genvar i;
generate
for (i = 6; i < 32; i = i + 1) begin : shift_oob_gen
or (oob[i], oob[i-1], S[i]);
end
endgenerate
wire [31:0] shifted; wire [31:0] shifted;
BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR); BARREL_SHIFTER32 shifter(shifted, D, S[4:0], LnR);
// return 0 if S >= 32 // return 0 if S >= 32
MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob[31]); MUX32_2x1 mux_oob(Y, shifted, 32'b0, oob);
endmodule endmodule