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lab-03: gate level model for 64-bit ripple carry adder and 32/64-bit twos complement

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Gate level implementation for the following components:
- RC_ADD_SUB_64
- TWOSCOMP64
- TWOSCOMP32
This commit is contained in:
Yuri Tatishchev 2024-10-02 16:18:00 -07:00
parent 42732e4fe0
commit 597e245641
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
1 changed files with 3 additions and 3 deletions
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6
logic.v
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@ -20,7 +20,7 @@ output [63:0] Y;
//input list //input list
input [63:0] A; input [63:0] A;
// TBD RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .A(64'b0), .B(A), .SnA(1'b1));
endmodule endmodule
@ -31,7 +31,7 @@ output [31:0] Y;
//input list //input list
input [31:0] A; input [31:0] A;
// TBD RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .A(0), .B(A), .SnA(1'b1));
endmodule endmodule
@ -143,4 +143,4 @@ input [1:0] I;
// TBD // TBD
endmodule endmodule