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lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement

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Yuri Tatishchev 2024-10-03 20:21:30 -07:00
parent bb7e172316
commit 48bdad0e8b
Signed by: CaZzzer
GPG Key ID: 28BE602058C08557
1 changed files with 1 additions and 14 deletions
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15
logic.v
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@ -21,7 +21,6 @@ output [63:0] Y;
input [63:0] A; input [63:0] A;
wire _CO; wire _CO;
RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(_CO), .A(64'b0), .B(A), .SnA(1'b1)); RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(_CO), .A(64'b0), .B(A), .SnA(1'b1));
endmodule endmodule
@ -33,19 +32,7 @@ output [31:0] Y;
//input list //input list
input [31:0] A; input [31:0] A;
// inverted bits
// wire A_inv[31:0];
//genvar i;
//generate
// for (i = 0; i < 32; i = i + 1)
// begin : inv32_gen_loop
// not (A_inv[i], A[i]);
// end
//endgenerate
wire _CO; wire _CO;
RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(_CO), .A(0), .B(A), .SnA(1'b1)); RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(_CO), .A(0), .B(A), .SnA(1'b1));
endmodule endmodule
@ -158,4 +145,4 @@ input [1:0] I;
// TBD // TBD
endmodule endmodule