From 48bdad0e8b1baa892a0e7c29f624d5cf4c684e27 Mon Sep 17 00:00:00 2001 From: Yuri Tatishchev Date: Thu, 3 Oct 2024 20:21:30 -0700 Subject: [PATCH] lab-03: 64-bit Ripple Carry Adder and 32/64-bit twos complement --- logic.v | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) diff --git a/logic.v b/logic.v index 0c53ea6..2c0bca2 100644 --- a/logic.v +++ b/logic.v @@ -21,7 +21,6 @@ output [63:0] Y; input [63:0] A; wire _CO; - RC_ADD_SUB_64 twoscomp64_sub(.Y(Y), .CO(_CO), .A(64'b0), .B(A), .SnA(1'b1)); endmodule @@ -33,19 +32,7 @@ output [31:0] Y; //input list input [31:0] A; -// inverted bits -// wire A_inv[31:0]; - -//genvar i; -//generate -// for (i = 0; i < 32; i = i + 1) -// begin : inv32_gen_loop -// not (A_inv[i], A[i]); -// end -//endgenerate - wire _CO; - RC_ADD_SUB_32 twoscomp32_sub(.Y(Y), .CO(_CO), .A(0), .B(A), .SnA(1'b1)); endmodule @@ -158,4 +145,4 @@ input [1:0] I; // TBD -endmodule \ No newline at end of file +endmodule