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da vinci tb: patch for smaller (20-bit) memory for faster tests

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This commit is contained in:
Yuri Tatishchev 2024-11-18 00:46:22 -08:00
parent 05c950a0f8
commit 2ffd8c9424
Signed by: CaZzzer
GPG Key ID: E0EBF441EA424369
6 changed files with 44 additions and 44 deletions
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12
TESTBENCH/da_vinci_tb.v
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@ -62,7 +62,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating fibonacci.dat\n", ""); $write("===> Done simulating fibonacci.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01000000, 'h0100000f); $writememh("./OUTPUT/fibonacci_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00040000, 'h0004000f);
/* END : test 1*/ /* END : test 1*/
end end
@ -78,7 +78,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating RevFib.dat\n", ""); $write("===> Done simulating RevFib.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff0, 'h03ffffff); $writememh("./OUTPUT/RevFib_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 'h0f, `INIT_STACK_POINTER);
/* END : test 2*/ /* END : test 2*/
end end
@ -94,7 +94,7 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating CS147_SP17_HW01_02.dat\n", ""); $write("===> Done simulating CS147_SP17_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h0100800A); $writememh("./OUTPUT/CS147_SP17_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h0004800A);
/* END : test 3*/ /* END : test 3*/
end end
@ -110,7 +110,7 @@ begin
#6000 $write("\n"); #6000 $write("\n");
$write("===> Done simulating CS147_FL15_HW01_02.dat\n", ""); $write("===> Done simulating CS147_FL15_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffff6, 'h03ffffff); $writememh("./OUTPUT/CS147_FL15_HW01_02_mem_dump.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 9, `INIT_STACK_POINTER);
/* END : test 4*/ /* END : test 4*/
end end
@ -126,8 +126,8 @@ begin
#5000 $write("\n"); #5000 $write("\n");
$write("===> Done simulating CS147_SP15_HW01_02.dat\n", ""); $write("===> Done simulating CS147_SP15_HW01_02.dat\n", "");
$write("\n"); $write("\n");
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h01008000, 'h01008005); $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_01.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h00048000, 'h00048005);
$writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, 'h03fffffA, 'h03ffffff); $writememh("./OUTPUT/CS147_SP15_HW01_02_mem_dump_02.dat", da_vinci_inst.memory_inst.memory_inst.sram_32x64m, `INIT_STACK_POINTER - 5, `INIT_STACK_POINTER);
/* END : test 5*/ /* END : test 5*/
end end
$stop; $stop;

44
TESTPROGRAM/CS147_FL15_HW01_02.dat
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@ -1,7 +1,7 @@
// ------ Program Part ---- // ------ Program Part ----
@0001000 @0001000
2021000A // addi r1, r1, 0xA; 2021000A // addi r1, r1, 0xA;
20421008 // addi r2, r2, 0x1008; 20420048 // addi r2, r2, 0x0048;
00401301 // sll r2, r2, 0xC; 00401301 // sll r2, r2, 0xC;
00411820 // add r3, r2, r1; 00411820 // add r3, r2, r1;
3C848000 // lui r4, r4, 0x8000; 3C848000 // lui r4, r4, 0x8000;
@ -21,25 +21,25 @@
// ------ Data Part ---- // ------ Data Part ----
@01008000 @00048000
005 // 01008000 005 // 0004 8000
008 // 01008001 008 // 0004 8001
009 // 01008002 009 // 0004 8002
010 // 01008003 010 // 0004 8003
020 // 01008004 020 // 0004 8004
029 // 01008005 029 // 0004 8005
02D // 01008006 02D // 0004 8006
02F // 01008007 02F // 0004 8007
032 // 01008008 032 // 0004 8008
037 // 01008009 037 // 0004 8009
002 // 0100800A 002 // 0004 800A
004 // 0100800B 004 // 0004 800B
008 // 0100800C 008 // 0004 800C
010 // 0100800D 010 // 0004 800D
020 // 0100800E 020 // 0004 800E
040 // 0100800F 040 // 0004 800F
080 // 01008010 080 // 0004 8010
100 // 01008011 100 // 0004 8011
200 // 01008012 200 // 0004 8012
400 // 01008013 400 // 0004 8013

2
TESTPROGRAM/CS147_SP15_HW01_02.dat
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@ -2,7 +2,7 @@
20000001 // addi r0, r0, 0x1; 20000001 // addi r0, r0, 0x1;
20210002 // addi r1, r1, 0x2; 20210002 // addi r1, r1, 0x2;
20420000 // addi r2, r2, 0x0; 20420000 // addi r2, r2, 0x0;
3C630100 // lui r3, 0x100; 3C630004 // lui r3, 0x0004;
34638000 // ori r3, r3, 0x8000; 34638000 // ori r3, r3, 0x8000;
20840005 // addi r4, r4, 0x5; 20840005 // addi r4, r4, 0x5;
00010020 // LOOP: add r0, r0, r1; 00010020 // LOOP: add r0, r0, r1;

24
TESTPROGRAM/CS147_SP17_HW01_02.dat
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@ -1,6 +1,6 @@
// ------ Program Part ---- // ------ Program Part ----
@0001000 @0001000
20001008 // addi r0, r0, 0x1008 20000048 // addi r0, r0, 0x0048
00000301 // sll r0, r0, 0xC 00000301 // sll r0, r0, 0xC
20420009 // addi r2, r2, 0x9 20420009 // addi r2, r2, 0x9
10410007 // LOOP: beq r1, r2, END 10410007 // LOOP: beq r1, r2, END
@ -14,15 +14,15 @@ AC050000 // sw r5, r0, 0x0
AC050000 // END: sw r5, r0, 0x0 AC050000 // END: sw r5, r0, 0x0
// ------ Data Part ---- // ------ Data Part ----
@01008000 @00048000
0A // 0100 8000 0A // 0004 8000
0B // 0100 8001 0B // 0004 8001
0C // 0100 8002 0C // 0004 8002
0D // 0100 8003 0D // 0004 8003
0E // 0100 8004 0E // 0004 8004
0F // 0100 8005 0F // 0004 8005
10 // 0100 8006 10 // 0004 8006
11 // 0100 8007 11 // 0004 8007
12 // 0100 8008 12 // 0004 8008
13 // 0100 8008 13 // 0004 8008

2
TESTPROGRAM/fibonacci.dat
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@ -1,6 +1,6 @@
@0001000 @0001000
20420001 // addi r2, r2, 0x0001; 20420001 // addi r2, r2, 0x0001;
3C000100 // lui r0, 0x0100; 3C000004 // lui r0, 0x0004;
AC010000 // sw r1, r0, 0x0000; AC010000 // sw r1, r0, 0x0000;
20000001 // loop: addi r0, r0, 0x0001; 20000001 // loop: addi r0, r0, 0x0001;
AC020000 // sw r2, r0, 0x0000; AC020000 // sw r2, r0, 0x0000;

4
prj_definition.v
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@ -23,7 +23,7 @@
`define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1) `define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1)
`define ADDRESS_WIDTH 26 `define ADDRESS_WIDTH 26
`define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1) `define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1)
`define MEM_SIZE (2 ** `ADDRESS_WIDTH) `define MEM_SIZE (2 ** (`ADDRESS_WIDTH - 6))
`define MEM_INDEX_LIMIT (`MEM_SIZE - 1) `define MEM_INDEX_LIMIT (`MEM_SIZE - 1)
`define NUM_OF_REG 32 `define NUM_OF_REG 32
`define REG_INDEX_LIMIT (`NUM_OF_REG -1) `define REG_INDEX_LIMIT (`NUM_OF_REG -1)
@ -41,4 +41,4 @@
// define ISA parameters // define ISA parameters
`define INST_START_ADDR 32'h00001000 `define INST_START_ADDR 32'h00001000
`define INIT_STACK_POINTER 32'h03ffffff `define INIT_STACK_POINTER 32'h000fffff