Iurii Tatishchev
42732e4fe0
Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32
76 lines
1.6 KiB
Verilog
76 lines
1.6 KiB
Verilog
// Name: rc_add_sub_32.v
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// Module: RC_ADD_SUB_32
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//
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// Output: Y : Output 32-bit
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// CO : Carry Out
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//
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//
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// Input: A : 32-bit input
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// B : 32-bit input
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// SnA : if SnA=0 it is add, subtraction otherwise
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//
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// Notes: 32-bit adder / subtractor implementaiton.
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module RC_ADD_SUB_64(Y, CO, A, B, SnA);
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// output list
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output [63:0] Y;
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output CO;
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// input list
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input [63:0] A;
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input [63:0] B;
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input SnA;
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// carry-in bits for each 1-bit full adder
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wire C[0:64];
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buf (C[0], SnA);
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genvar i;
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generate
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for (i = 0; i < 64; i = i + 1)
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begin : add64_gen_loop
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wire B_xor;
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xor (B_xor, B[i], SnA);
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FULL_ADDER add64_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
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end
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endgenerate
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buf (CO, C[64]);
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endmodule
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module RC_ADD_SUB_32(Y, CO, A, B, SnA);
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// output list
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output [`DATA_INDEX_LIMIT:0] Y;
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output CO;
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// input list
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input [`DATA_INDEX_LIMIT:0] A;
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input [`DATA_INDEX_LIMIT:0] B;
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input SnA;
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// carry-in bits for each 1-bit full adder
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wire C[0:32];
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buf (C[0], SnA);
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genvar i;
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generate
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for (i = 0; i < 32; i = i + 1)
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begin : add32_gen_loop
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wire B_xor;
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xor (B_xor, B[i], SnA);
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FULL_ADDER add32_inst(Y[i], C[i+1], A[i], B_xor, C[i]);
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end
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endgenerate
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buf (CO, C[32]);
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endmodule
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