45 lines
1.3 KiB
Verilog
45 lines
1.3 KiB
Verilog
// Name: prj_definition.v
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// Module:
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// Input:
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// Output:
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//
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// Notes: Common definitions
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 02, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`timescale 1ns/10ps
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`define SYS_CLK_PERIOD 10
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`define SYS_CLK_HALF_PERIOD (`SYS_CLK_PERIOD/2)
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`define DATA_WIDTH 32
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`define DATA_INDEX_LIMIT (`DATA_WIDTH -1)
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`define ALU_OPRN_WIDTH 6
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`define ALU_OPRN_INDEX_LIMIT (`ALU_OPRN_WIDTH -1)
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`define ADDRESS_WIDTH 26
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`define ADDRESS_INDEX_LIMIT (`ADDRESS_WIDTH -1)
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`define MEM_SIZE (2 ** (`ADDRESS_WIDTH - 6))
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`define MEM_INDEX_LIMIT (`MEM_SIZE - 1)
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`define NUM_OF_REG 32
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`define REG_INDEX_LIMIT (`NUM_OF_REG -1)
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`define REG_ADDR_INDEX_LIMIT 4
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`define CTRL_WIDTH 32
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`define CTRL_WIDTH_INDEX_LIMIT (`CTRL_WIDTH - 1)
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`define DOUBLE_DATA_WIDTH 64
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`define DOUBLE_DATA_INDEX_LIMIT (`DOUBLE_DATA_WIDTH - 1)
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// definition for processor state
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`define PROC_FETCH 3'h0
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`define PROC_DECODE 3'h1
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`define PROC_EXE 3'h2
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`define PROC_MEM 3'h3
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`define PROC_WB 3'h4
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// define ISA parameters
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`define INST_START_ADDR 32'h00001000
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`define INIT_STACK_POINTER 32'h000fffff
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