Iurii Tatishchev
42732e4fe0
Gate level implementation for the following components: - FULL_ADDER - HALF_ADDER - RC_ADD_SUB_32
32 lines
762 B
Verilog
32 lines
762 B
Verilog
// Name: full_adder.v
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// Module: FULL_ADDER
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//
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// Output: S : Sum
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// CO : Carry Out
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//
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// Input: A : Bit 1
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// B : Bit 2
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// CI : Carry In
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//
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// Notes: 1-bit full adder implementaiton.
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//
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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`include "prj_definition.v"
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module FULL_ADDER(S,CO,A,B, CI);
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output S,CO;
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input A,B, CI;
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wire Y, CO1, CO2;
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HALF_ADDER ha1(.Y(Y), .C(CO1), .A(A), .B(B));
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HALF_ADDER ha2(.Y(S), .C(CO2), .A(Y), .B(CI));
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or (CO, CO1, CO2);
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endmodule
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