132 lines
4.8 KiB
Verilog
132 lines
4.8 KiB
Verilog
// Name: data_path.v
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// Module: DATA_PATH
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// Output: DATA : Data to be written at address ADDR
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// ADDR : Address of the memory location to be accessed
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//
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// Input: DATA : Data read out in the read operation
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// CLK : Clock signal
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// RST : Reset signal
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//
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// Notes: - 32 bit processor implementing cs147sec05 instruction set
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//
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// Revision History:
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//
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// Version Date Who email note
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//------------------------------------------------------------------------------------------
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// 1.0 Sep 10, 2014 Kaushik Patra kpatra@sjsu.edu Initial creation
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//------------------------------------------------------------------------------------------
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//
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`include "prj_definition.v"
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`include "control_unit.v" // for control signal index macros
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module DATA_PATH(DATA_OUT, ADDR, ZERO, INSTRUCTION, DATA_IN, CTRL, CLK, RST);
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// output list
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output [`ADDRESS_INDEX_LIMIT:0] ADDR;
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output ZERO;
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output [`DATA_INDEX_LIMIT:0] DATA_OUT, INSTRUCTION;
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// input list
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input [`CTRL_WIDTH_INDEX_LIMIT:0] CTRL;
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input CLK, RST;
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input [`DATA_INDEX_LIMIT:0] DATA_IN;
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// variables
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wire [31:0] ir; // Instruction Register
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wire [31:0] r1, r2; // Register File
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wire [31:0] pc, pc_inc; // Program Counter
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wire [31:0] sp; // Stack Pointer
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wire [31:0] alu_out; // ALU output
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// instruction sent to control unit
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buf ir_buf [31:0] (INSTRUCTION, ir);
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// Parse the instruction data
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wire [5:0] opcode;
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wire [4:0] rs;
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wire [4:0] rt;
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wire [4:0] rd;
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wire [4:0] shamt;
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wire [5:0] funct;
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wire [15:0] imm;
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wire [25:0] addr;
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// common for all
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buf opcode_buf [5:0] (opcode, ir[31:26]);
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// common for R-type, I-type
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buf rs_buf [4:0] (rs, ir[25:21]);
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buf rt_buf [4:0] (rt, ir[20:16]);
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// for R-type
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buf rd_buf [4:0] (rd, ir[15:11]);
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buf shamt_buf [4:0] (shamt, ir[10:6]);
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buf funct_buf [5:0] (funct, ir[5:0]);
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// for I-type
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buf imm_buf [15:0] (imm, ir[15:0]);
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// for J-type
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buf addr_buf [25:0] (addr, ir[25:0]);
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// Instruction Register
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D_LATCH32 ir_inst(.Q(ir), .D(DATA_IN), .LOAD(CTRL[`ir_load]), .RESET(RST));
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// Register File Input
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wire [31:0] r1_sel, wa_sel, wd_sel;
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wire [31:0] wa_sel_p1, wa_sel_p2, wd_sel_p1, wd_sel_p2;
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wire [31:0] imm_zx_lsb;
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buf imm_zx_lsb_buf [31:0] (imm_zx_lsb, {imm, 16'b0});
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MUX32_2x1 mux_r1_sel(r1_sel, {27'b0,rs}, 32'b0, CTRL[`r1_sel_1]);
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MUX32_2x1 mux_wa_sel_p1(wa_sel_p1, {27'b0,rd}, {27'b0,rt}, CTRL[`wa_sel_1]);
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// 0 for push/pop, 31 for jal
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MUX32_2x1 mux_wa_sel_p2(wa_sel_p2, 32'b0, 31, CTRL[`wa_sel_2]);
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MUX32_2x1 mux_wa_sel(wa_sel, wa_sel_p2, wa_sel_p1, CTRL[`wa_sel_3]);
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MUX32_2x1 mux_wd_sel_p1(wd_sel_p1, alu_out,DATA_IN, CTRL[`wd_sel_1]);
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MUX32_2x1 mux_wd_sel_p2(wd_sel_p2, wd_sel_p1, imm_zx_lsb, CTRL[`wd_sel_2]);
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MUX32_2x1 mux_wd_sel(wd_sel, pc_inc, wd_sel_p2, CTRL[`wd_sel_3]);
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// Register File
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REGISTER_FILE_32x32 rf_inst(.DATA_R1(r1), .DATA_R2(r2), .ADDR_R1(r1_sel[4:0]), .ADDR_R2(rt),
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.DATA_W(wd_sel), .ADDR_W(wa_sel[4:0]), .READ(CTRL[`reg_r]), .WRITE(CTRL[`reg_w]),
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.CLK(CLK), .RST(RST));
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// ALU Input
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wire [31:0] op1_sel, op2_sel;
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wire [31:0] op2_sel_p1, op2_sel_p2, op2_sel_p3;
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wire [31:0] shamt_zx, imm_sx, imm_zx;
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buf shamt_zx_buf [31:0] (shamt_zx, {27'b0, shamt});
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buf imm_sx_buf [31:0] (imm_sx, {{16{imm[15]}}, imm});
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buf imm_zx_buf [31:0] (imm_zx, {16'b0, imm});
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MUX32_2x1 mux_op1_sel(op1_sel, r1, sp, CTRL[`op1_sel_1]);
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MUX32_2x1 mux_op2_sel_p1(op2_sel_p1, 32'b1, shamt_zx, CTRL[`op2_sel_1]);
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MUX32_2x1 mux_op2_sel_p2(op2_sel_p2, imm_zx, imm_sx, CTRL[`op2_sel_2]);
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MUX32_2x1 mux_op2_sel_p3(op2_sel_p3, op2_sel_p2, op2_sel_p1, CTRL[`op2_sel_3]);
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MUX32_2x1 mux_op2_sel(op2_sel, op2_sel_p3, r2, CTRL[`op2_sel_4]);
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// ALU
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ALU alu_inst(.OUT(alu_out), .ZERO(ZERO), .OP1(op1_sel), .OP2(op2_sel), .OPRN(CTRL[`alu_oprn]));
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// Progam Counter Input
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wire [31:0] pc_sel;
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wire [31:0] pc_branch, pc_jump, pc_sel_p1, pc_sel_p2;
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RC_ADD_SUB_32 pc_inc_inst(.Y(pc_inc), .CO(), .A(pc), .B(32'b1), .SnA(1'b0));
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MUX32_2x1 mux_pc_sel_p1(pc_sel_p1, r1, pc_inc, CTRL[`pc_sel_1]);
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RC_ADD_SUB_32 pc_sel_2_inst(.Y(pc_branch), .CO(), .A(pc_inc), .B(imm_sx), .SnA(1'b0));
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MUX32_2x1 mux_pc_sel_p2(pc_sel_p2, pc_sel_p1, pc_branch, CTRL[`pc_sel_2]);
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buf pc_jump_buf [31:0] (pc_jump, {6'b0, addr});
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MUX32_2x1 mux_pc_sel(pc_sel, pc_jump, pc_sel_p2, CTRL[`pc_sel_3]);
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// Program Counter
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defparam pc_inst.PATTERN = `INST_START_ADDR;
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REG32_PP pc_inst(.Q(pc), .D(pc_sel), .LOAD(CTRL[`pc_load]), .CLK(CLK), .RESET(RST));
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// Stack Pointer
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defparam sp_inst.PATTERN = `INIT_STACK_POINTER;
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REG32_PP sp_inst(.Q(sp), .D(alu_out), .LOAD(CTRL[`sp_load]), .CLK(CLK), .RESET(RST));
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// Data out
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MUX32_2x1 mux_data_out(DATA_OUT, r2, r1, CTRL[`md_sel_1]);
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// Address out
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wire [31:0] ma_sel_p1;
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MUX32_2x1 mux_ma_sel_p1(ma_sel_p1, alu_out, sp, CTRL[`ma_sel_1]);
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// discard the upper 6 bits of the address since it's only 26 bit addressable
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(* keep="soft" *)
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wire [5:0] _addr_ignored;
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MUX32_2x1 mux_ma_sel({_addr_ignored,ADDR}, ma_sel_p1, pc, CTRL[`ma_sel_2]);
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endmodule
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