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2 Commits
project ... 02781c283f

Author SHA1 Message Date
Yuri Tatishchev
02781c283f project: add da vinci test programs 2024-11-16 16:49:44 -08:00
Yuri Tatishchev
88b635122f (WIP) control unit: initial implementation of things 2024-11-12 18:02:06 -08:00
25 changed files with 673 additions and 6 deletions
Expand all files Collapse all files

4
.gitignore vendored
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@@ -27,3 +27,7 @@ sc_dpiheader.h
vsim.dbg vsim.dbg
# End of https://www.toptal.com/developers/gitignore/api/modelsim # End of https://www.toptal.com/developers/gitignore/api/modelsim
!TESTPROGRAM/*.dat
!GOLDEN/*.dat
!OUTPUT/*.dat

13
GOLDEN/CS147_FL15_HW01_02_mem_dump_golden.dat Normal file
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@@ -0,0 +1,13 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000020
00000020
00000010
00000010
00000009
00000008
00000008
00000005
00000004
00000002

9
GOLDEN/CS147_SP15_HW01_02_mem_dump_01_golden.dat Normal file
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@@ -0,0 +1,9 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000001
00000004
00000004
00000010
00000010
00000000

9
GOLDEN/CS147_SP15_HW01_02_mem_dump_02_golden.dat Normal file
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@@ -0,0 +1,9 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000020
00000008
00000008
00000002
00000002

14
GOLDEN/CS147_SP17_HW01_02_mem_dump_golden.dat Normal file
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@@ -0,0 +1,14 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000015
00000017
00000019
0000001b
0000001d
0000001f
00000021
00000023
00000025
00000025
00000000

19
GOLDEN/RevFib_mem_dump.golden.dat Normal file
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@@ -0,0 +1,19 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
ffffffc9
00000022
ffffffeb
0000000d
fffffff8
00000005
fffffffd
00000002
ffffffff
00000001
00000000
00000001
00000001
00000002
00000003
00000005

19
GOLDEN/fibonacci_mem_dump.golden.dat Normal file
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@@ -0,0 +1,19 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000001
00000002
00000003
00000005
00000008
0000000d
00000015
00000022
00000037
00000059
00000090
000000e9
00000179
00000262

13
OUTPUT/CS147_FL15_HW01_02_mem_dump.dat Normal file
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@@ -0,0 +1,13 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

14
OUTPUT/CS147_SP17_HW01_02_mem_dump.dat Normal file
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@@ -0,0 +1,14 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000000a
0000000b
0000000c
0000000d
0000000e
0000000f
00000010
00000011
00000012
00000013
00000000

19
OUTPUT/RevFib_mem_dump.dat Normal file
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@@ -0,0 +1,19 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

19
OUTPUT/fibonacci_mem_dump.dat Normal file
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@@ -0,0 +1,19 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/DA_VINCI_TB/da_vinci_inst/memory_inst/memory_inst/sram_32x64m
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000

11
OUTPUT/full_adder.out Normal file
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@@ -0,0 +1,11 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/FULL_ADDER_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000001
00000002
00000001
00000002
00000002
00000003

7
OUTPUT/half_adder.out Normal file
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@@ -0,0 +1,7 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/HALF_ADDER_TB/results
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000
00000001
00000001
00000002

11
OUTPUT/mult32_tb.out Normal file
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@@ -0,0 +1,11 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/MULT_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000000000c8
000000000000002d
ffffffffffffff90
ffffffffffffff42
3100000000000000
cf00000000000000
cf00000000000000
3100000000000000

8
OUTPUT/mult32_u_tb.out Normal file
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@@ -0,0 +1,8 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/MULT_U_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
00000000000000c8
000000000000002d
0000000000000070
00000000000000be
006975a0b62bf524

8
OUTPUT/rc_add_sub_32.out Normal file
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@@ -0,0 +1,8 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/RC_ADD_SUB_32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
0000001e
fffffff6
00000003
00000004
00005555

5
OUTPUT/twoscomp32_tb.out Normal file
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@@ -0,0 +1,5 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/TWOSCOMP32_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
fffffff6
00000005

5
OUTPUT/twoscomp64_tb.out Normal file
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@@ -0,0 +1,5 @@
// memory data file (do not edit the following line - required for mem load use)
// instance=/TWOSCOMP64_TB/result
// format=hex addressradix=h dataradix=h version=1.0 wordsperline=1 noaddress
fffffffffffffff6
0000000000000005

45
TESTPROGRAM/CS147_FL15_HW01_02.dat Normal file
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@@ -0,0 +1,45 @@
// ------ Program Part ----
@0001000
2021000A // addi r1, r1, 0xA;
20421008 // addi r2, r2, 0x1008;
00401301 // sll r2, r2, 0xC;
00411820 // add r3, r2, r1;
3C848000 // lui r4, r4, 0x8000;
8C450000 // LOOP: lw r5, r2,0x0;
8C660000 // lw r6, r3, 0x0;
00A63822 // sub r7, r5, r6;
00E44024 // and r8, r7, r4;
15280003 // bne r8, r9, L1;
20C00000 // addi r0, r6, 0x0;
20630001 // addi r3, r3, 0x1;
0800100F // jmp L2;
20A00000 // L1: addi r0, r5, 0x0;
20420001 // addi r2, r2, 0x1;
6C000000 // L2: push
2021FFFF // addi r1, r1, 0xFFFF;
1521FFF3 // bne r1, r9, LOOP;
// ------ Data Part ----
@01008000
005 // 01008000
008 // 01008001
009 // 01008002
010 // 01008003
020 // 01008004
029 // 01008005
02D // 01008006
02F // 01008007
032 // 01008008
037 // 01008009
002 // 0100800A
004 // 0100800B
008 // 0100800C
010 // 0100800D
020 // 0100800E
040 // 0100800F
080 // 01008010
100 // 01008011
200 // 01008012
400 // 01008013

21
TESTPROGRAM/CS147_SP15_HW01_02.dat Normal file
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@@ -0,0 +1,21 @@
@0001000
20000001 // addi r0, r0, 0x1;
20210002 // addi r1, r1, 0x2;
20420000 // addi r2, r2, 0x0;
3C630100 // lui r3, 0x100;
34638000 // ori r3, r3, 0x8000;
20840005 // addi r4, r4, 0x5;
00010020 // LOOP: add r0, r0, r1;
00010822 // sub r1, r0, r1;
00010022 // sub r0, r0, r1;
AC610000 // sw r1, r3, 0x0;
20630001 // addi r3, r3, 0x1;
6C000000 // push;
00000041 // sll r0, r0, 0x1;
00200841 // sll r1, r1, 0x1;
20420001 // addi r2, r2, 0x1;
1482FFF6 // bne r2, r4, LOOP;

28
TESTPROGRAM/CS147_SP17_HW01_02.dat Normal file
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@@ -0,0 +1,28 @@
// ------ Program Part ----
@0001000
20001008 // addi r0, r0, 0x1008
00000301 // sll r0, r0, 0xC
20420009 // addi r2, r2, 0x9
10410007 // LOOP: beq r1, r2, END
8C030000 // lw r3, r0, 0x0
8C040001 // lw r4, r0, 0x1
00642820 // add r5, r3, r4
AC050000 // sw r5, r0, 0x0
20000001 // addi r0, r0, 0x1
20210001 // addi r1, r1, 0x1
08001003 // j LOOP
AC050000 // END: sw r5, r0, 0x0
// ------ Data Part ----
@01008000
0A // 0100 8000
0B // 0100 8001
0C // 0100 8002
0D // 0100 8003
0E // 0100 8004
0F // 0100 8005
10 // 0100 8006
11 // 0100 8007
12 // 0100 8008
13 // 0100 8008

16
TESTPROGRAM/RevFib.dat Normal file
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@@ -0,0 +1,16 @@
@0001000
20210005 // addi r1, r1, 0x5
20420003 // addi r2, r2, 0x3
20200000 // addi r0, r1, 0x0
6c000000 // push
20400000 // loop : addi r0, r2, 0x0
6c000000 // push
20430000 // addi r3, r2, 0x0
00221022 // sub r2, r1, r2
20610000 // addi r1, r3, 0x0
08001004 // jmp loop
00000000 // nop
00000000 // nop

13
TESTPROGRAM/fibonacci.dat Normal file
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@@ -0,0 +1,13 @@
@0001000
20420001 // addi r2, r2, 0x0001;
3C000100 // lui r0, 0x0100;
AC010000 // sw r1, r0, 0x0000;
20000001 // loop: addi r0, r0, 0x0001;
AC020000 // sw r2, r0, 0x0000;
20430000 // addi r3, r2, 0x0000;
00411020 // add r2, r2, r1;
20610000 // addi r1, r3, 0x0000;
08001003 // jmp loop;

11
TESTPROGRAM/mem_content_01.dat Normal file
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@@ -0,0 +1,11 @@
@0001000
00414020 00414021 00414022 00414023 // sample data
00414024 00414025 00414026 00414027
00414028 00414029 0041402a 0041402b
0041402c 0041402d 0041402e 0041402f
@002f00a
00514020 00514021 00514022 00514023
00514024 00514025 00514026 00514027
00514028 00514029 0051402a 0051402b
0051402c 0051402d 0051402e 0051402f

326
control_unit.v
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@@ -27,7 +27,314 @@ output READ, WRITE;
input ZERO, CLK, RST; input ZERO, CLK, RST;
input [`DATA_INDEX_LIMIT:0] INSTRUCTION; input [`DATA_INDEX_LIMIT:0] INSTRUCTION;
task print_instruction;
input [`DATA_INDEX_LIMIT:0] inst;
reg [5:0] opcode2;
reg [4:0] rs2;
reg [4:0] rt2;
reg [4:0] rd2;
reg [4:0] shamt2;
reg [5:0] funct2;
reg [15:0] immediate2;
reg [25:0] address2;
begin
// parse the instruction
// R-type
{opcode2, rs2, rt2, rd2, shamt2, funct2} = inst;
// I-type
{opcode2, rs2, rt2, immediate2 } = inst;
// J-type
{opcode2, address2} = inst;
$write("@ %6dns -> [0X%08h] ", $time, inst);
case(opcode2)
// R-Type
6'h00 : begin
case(funct2)
6'h20: $write("add r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h22: $write("sub r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h2c: $write("mul r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h24: $write("and r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h25: $write("or r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h27: $write("nor r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h2a: $write("slt r[%02d], r[%02d], r[%02d];", rd2, rs2, rt2);
6'h01: $write("sll r[%02d], r[%02d], %2d;", rd2, rs2, shamt2);
6'h02: $write("srl r[%02d], 0X%02h, r[%02d];", rd2, rs2, shamt2);
6'h08: $write("jr r[%02d];", rs2);
default: begin $write("");
end
endcase
end
// I-type
6'h08 : $write("addi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h1d : $write("muli r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h0c : $write("andi r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h0d : $write("ori r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h0f : $write("lui r[%02d], 0X%04h;", rt2, immediate2);
6'h0a : $write("slti r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h04 : $write("beq r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h05 : $write("bne r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h23 : $write("lw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
6'h2b : $write("sw r[%02d], r[%02d], 0X%04h;", rt2, rs2, immediate2);
// J-Type
6'h02 : $write("jmp 0X%07h;", address2);
6'h03 : $write("jal 0X%07h;", address2);
6'h1b : $write("push;");
6'h1c : $write("pop;");
default: $write("");
endcase
$write("\n");
end
endtask
//------------------------------------- END ---------------------------------------//
reg read, write;
assign READ = read;
assign WRITE = write;
// Control signals, same as in data_path.v
reg pc_load, pc_sel_1, pc_sel_2, pc_sel_3,
ir_load, reg_r, reg_w,
r1_sel_1, wa_sel_1, wa_sel_2, wa_sel_3,
sp_load, op1_sel_1,
op2_sel_1, op2_sel_2, op2_sel_3, op2_sel_4,
wd_sel_1, wd_sel_2, wd_sel_3,
ma_sel_1, ma_sel_2,
md_sel_1;
reg [5:0] alu_oprn;
buf (CTRL[0], pc_load);
buf (CTRL[1], pc_sel_1);
buf (CTRL[2], pc_sel_2);
buf (CTRL[3], pc_sel_3);
buf (CTRL[4], ir_load);
buf (CTRL[5], reg_r);
buf (CTRL[6], reg_w);
buf (CTRL[7], r1_sel_1);
buf (CTRL[8], wa_sel_1);
buf (CTRL[9], wa_sel_2);
buf (CTRL[10], wa_sel_3);
buf (CTRL[11], sp_load);
buf (CTRL[12], op1_sel_1);
buf (CTRL[13], op2_sel_1);
buf (CTRL[14], op2_sel_2);
buf (CTRL[15], op2_sel_3);
buf (CTRL[16], op2_sel_4);
buf (CTRL[17], wd_sel_1);
buf (CTRL[18], wd_sel_2);
buf (CTRL[19], wd_sel_3);
buf (CTRL[20], ma_sel_1);
buf (CTRL[21], ma_sel_2);
buf (CTRL[22], md_sel_1);
buf alu_oprn_buf [5:0] (CTRL[28:23], alu_oprn);
// Parse the instruction data, same as in data_path.v
wire [5:0] opcode;
wire [4:0] rs;
wire [4:0] rt;
wire [4:0] rd;
wire [4:0] shamt;
wire [5:0] funct;
wire [15:0] imm;
wire [25:0] addr;
// common for all
buf opcode_buf [5:0] (opcode, INSTRUCTION[31:26]);
// common for R-type, I-type
buf rs_buf [4:0] (rs, INSTRUCTION[25:21]);
buf rt_buf [4:0] (rt, INSTRUCTION[20:16]);
// for R-type
buf rd_buf [4:0] (rd, INSTRUCTION[15:11]);
buf shamt_buf [4:0] (shamt, INSTRUCTION[10:6]);
buf funct_buf [5:0] (funct, INSTRUCTION[5:0]);
// for I-type
buf imm_buf [15:0] (imm, INSTRUCTION[15:0]);
// for J-type
buf addr_buf [25:0] (addr, INSTRUCTION[25:0]);
// State machine
wire [2:0] state;
PROC_SM proc_sm(state, CLK, RST);
// TBD - take action on each +ve edge of clock // TBD - take action on each +ve edge of clock
always @ (state) begin
// Print current state
$write("@ %6dns -> ", $time);
$write("STATE ", state, ": ");
case (state)
`PROC_FETCH: $write("FETCH");
`PROC_DECODE: $write("DECODE");
`PROC_EXE: $write("EXECUTE");
`PROC_MEM: $write("MEMORY");
`PROC_WB: $write("WRITE BACK");
default: $write("INVALID");
endcase
case (state)
// fetch - next instruction from memory at PC
`PROC_FETCH: begin
// loaded in previous state, set to 0
pc_load = 1'b0;
reg_r = 1'b0;
reg_w = 1'b0;
// load now
ir_load = 1'b1;
read = 1'b1;
write = 1'b0;
// selections
// ma_sel_2 - load data from mem[PC]
ma_sel_2 = 1'b1;
end
// decode - parse instruction and read values from register file
`PROC_DECODE: begin
// loaded in previous state, set to 0
ir_load = 1'b0;
sp_load = 1'b0;
read = 1'b0;
// load now
reg_r = 1'b1;
reg_w = 1'b0;
// selections
// r1_sel_1: push - store value of r0 at stack pointer
r1_sel_1 = opcode != 6'h1b ? 1'b0 : 1'b1;
// wa_sel_1: R-type - write to rd, I-type - write to rt
wa_sel_1 = opcode == 6'h00 ? 1'b0 : 1'b1;
// wa_sel_2: jal - write to r31, pop - write to r0
wa_sel_2 = opcode == 6'h03 ? 1'b1 : 1'b0;
// wa_sel_3: push or pop - wa_sel_2, else wa_sel_1
wa_sel_3 = opcode == 6'h03 || opcode == 6'h1c ? 1'b0 : 1'b1;
// jr - jump to address in register
pc_sel_1 = opcode == 6'h00 && funct == 6'h08 ? 1'b0 : 1'b1;
// beq, bne - branch if equal or not equal
// TODO: this should only be selected if the condition is met
// pc_sel_2 = opcode == 6'h04 || opcode == 6'h05 ? 1'b1 : 1'b0;
// jmp, jal - jump to address
pc_sel_3 = opcode == 6'h02 || opcode == 6'h03 ? 1'b0 : 1'b1;
// alu_oprn - operation to be performed by ALU
// R-type
if (opcode == 6'h00) begin
case (funct)
6'h20: alu_oprn = 6'h01; // add
6'h22: alu_oprn = 6'h02; // sub
6'h2c: alu_oprn = 6'h03; // mul
6'h02: alu_oprn = 6'h04; // srl
6'h01: alu_oprn = 6'h05; // sll
6'h24: alu_oprn = 6'h06; // and
6'h25: alu_oprn = 6'h07; // or
6'h27: alu_oprn = 6'h08; // nor
6'h2a: alu_oprn = 6'h09; // slt
default: alu_oprn = 6'hxx;
endcase
end
// I-type and J-type
else begin
case (opcode)
// I-type
6'h08: alu_oprn = 6'h01; // addi
6'h1d: alu_oprn = 6'h03; // muli
6'h0c: alu_oprn = 6'h06; // andi
6'h0d: alu_oprn = 6'h07; // ori
6'h0a: alu_oprn = 6'h09; // slti
6'h04: alu_oprn = 6'h02; // beq - sub
6'h05: alu_oprn = 6'h02; // bne - sub
6'h23: alu_oprn = 6'h01; // lw - add
6'h2b: alu_oprn = 6'h01; // sw - add
// J-type
6'h1b: alu_oprn = 6'h02; // push - sub
6'h1c: alu_oprn = 6'h01; // pop - add
default: alu_oprn = 6'hxx;
endcase
end
// op1_sel_1 - select r1 or sp based on opcode
// push or pop - sp, else r1
op1_sel_1 = opcode == 6'h1b || opcode == 6'h1c ? 1'b1 : 1'b0;
// op2_sel_1 - select 1 or shamt based on alu_oprn
// sll or srl - shamt, else 1 (for increments/decrements)
op2_sel_1 = alu_oprn == 6'h04 || alu_oprn == 6'h05 ? 1'b1 : 1'b0;
// op2_sel_2 - select imm_zx or imm_sx based on alu_oprn
// logical (and, or) - imm_zx, else imm_sx; ('nor' not availble in I-type)
op2_sel_2 = alu_oprn == 6'h06 || alu_oprn == 6'h07 ? 1'b0 : 1'b1;
// op2_sel_3 - select op2_sel_2 or op2_sel_1 based on alu_oprn
// R-type - op2_sel_1, I-type - op2_sel_2
op2_sel_3 = opcode == 6'h00 ? 1'b1 : 1'b0;
// op2_sel_4 - select op2_sel_3 or r2
// I-type or shift or inc/dec - op2_sel_3, else r2
// i.e. r2 only if R-type and not shift
op2_sel_4 = opcode != 6'h00 || alu_oprn == 6'h04 || alu_oprn == 6'h05 ? 1'b0 : 1'b1;
end
// execute - perform operation based on instruction
`PROC_EXE: begin
// selections
// wd_sel_1 - alu_out or DATA_IN
wd_sel_1 = 1'b0;
// wd_sel_2 - wd_sel_1 or imm_zx_lsb
// lui - imm_zx_lsb, else wd_sel_1
wd_sel_2 = opcode == 6'h0f ? 1'b1 : 1'b0;
// wd_sel_3 - pc_inc or wd_sel_2
// jal - pc_inc, else wd_sel_2
wd_sel_3 = opcode == 6'h03 ? 1'b0 : 1'b1;
// md_sel_1 - r1 for push, r2 for sw
md_sel_1 = opcode == 6'h1b ? 1'b1 : 1'b0;
end
`PROC_MEM: begin
// load now
// push or sw - write to memory
if (opcode == 6'h1b || opcode == 6'h2b) begin
read = 1'b0;
write = 1'b1;
end
else begin
read = 1'b1;
write = 1'b0;
end
end
`PROC_WB: begin
// loaded in previous state, set to 0
read = 1'b0;
write = 1'b0;
// load now
pc_load = 1'b1;
// write to register file if
// R-type (except jr) or I-type (except beq, bne, sw) or pop or jal
reg_w = (opcode == 6'h00 && funct != 6'h08) // R-type (except jr)
|| (opcode == 6'h08 || opcode == 6'h1d || opcode == 6'h0c || opcode == 6'h0d
|| opcode == 6'h0f || opcode == 6'h0a || opcode == 6'h23) // I-type (except beq, bne, sw)
|| (opcode == 6'h1c || opcode == 6'h03) // pop or jal
? 1'b1 : 1'b0;
// selections
// ma_sel_2 - load data from mem[PC]
ma_sel_2 = 1'b1;
// pc_sel_2 - branch if equal or not equal
pc_sel_2 = (opcode == 6'h04 && ZERO) || (opcode == 6'h05 && ~ZERO) ? 1'b1 : 1'b0;
end
default: begin
$write("@ %6dns -> ", $time);
$write("STATE ", state, ": ");
$write("INVALID");
print_instruction(INSTRUCTION);
end
endcase
// TBD - assign control signals based on instruction
print_instruction(INSTRUCTION);
// TBD - assign READ and WRITE signals based on instruction
end
endmodule endmodule
@@ -56,6 +363,25 @@ input CLK, RST;
// list of outputs // list of outputs
output [2:0] STATE; output [2:0] STATE;
reg [2:0] state_sel = 3'bxxx;
always @ (negedge RST) begin
// set to invalid value, so that it defaults to fetch
state_sel = 3'bxxx;
end
// TBD - take action on each +ve edge of clock // TBD - take action on each +ve edge of clock
always @ (posedge CLK) begin
case (state_sel)
`PROC_FETCH: state_sel = `PROC_DECODE;
`PROC_DECODE: state_sel = `PROC_EXE;
`PROC_EXE: state_sel = `PROC_MEM;
`PROC_MEM: state_sel = `PROC_WB;
`PROC_WB: state_sel = `PROC_FETCH;
default: state_sel = `PROC_FETCH;
endcase
end
assign STATE = state_sel;
endmodule endmodule